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ATT3030

Field-Programmable Gate Arrays

Unspecified 

ATT3000 Series Field-Programmable Gate Arrays

Data Sheet

February 1997

Pin Information

Table 4. Permanently Dedicated Pins

Symbol

VCC

GND

PWRDWN

RESET

CCLK

DONE/

PROG

M0/RTRIG

M1/RDATA

Name/Description

Two to eight (depending on package type) connections to the nominal +5 V supply voltage. All

must be connected.

Two to eight (depending on package type) connections to ground. All must be connected.

A low on this CMOS compatible input stops all internal activity to minimize VCC power, and puts

all output buffers in a high-impedance state; configuration is retained. When the PWRDWN pin

returns high, the device returns to operation with the same sequence of buffer enable and

DONE/PROG as at the completion of configuration. All internal storage elements are reset. If

not used, PWRDWN must be tied to VCC.

This is an active-low input which has three functions:

s Prior to the start of configuration, a low input will delay the start of the configuration process.

An internal circuit senses the application of power and begins a minimal time-out cycle. When

the time-out and RESET are complete, the levels of the M lines are sampled and configuration

begins.

s If RESET is asserted during a configuration, the FPGA is reinitialized and will restart the con-

figuration at the termination of RESET.

s If RESET is asserted after configuration is complete, it will provide an asynchronous reset of all

IOB and CLB storage elements of the FPGA.

Configuration Clock. During configuration, this is an output of an FPGA in master mode or

peripheral mode. FPGAs in slave mode use it as a clock input. During a readback operation, it is

a clock input for the configuration data being filtered out.

DONE Output. Configurable as open drain with or without an internal pull-up resistor. At the

completion of configuration, the circuitry of the FPGA becomes active in a synchronous order,

and DONE may be programmed to occur one cycle before or after that occurs. Once configura-

tion is done, a high-to-low transition of this pin will cause an initialization of the FPGA and start a

reconfiguration.

Mode 0. This input, M1, and M2 are sampled before the start of configuration to establish the

configuration mode to be used. After configuration is complete, a low-to-high transition acts as a

read trigger to initiate a readback of configuration and storage-element data clocked by CCLK.

Mode 1. This input, M0, and M2 are sampled before the start of configuration to establish the

configuration mode to be used. After configuration is complete, this pin is the active-low output of

the readback data.

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Lucent Technologies Inc.

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