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ATT3030

Field-Programmable Gate Arrays

Unspecified 

ATT3000 Series Field-Programmable Gate Arrays

Data Sheet

February 1997

Power

Power Distribution

Power for the FPGA is distributed through a grid to

achieve high noise immunity and isolation between

logic and I/O. Inside the FPGA, a dedicated VCC and

ground ring surrounding the logic array provides power

to the I/O drivers (see Figure 31 below). An indepen-

dent matrix of VCC and ground lines supplies the inte-

rior logic of the device. This power distribution grid

provides a stable supply and ground for all internal

logic, provided that the external package power pins

are all connected and appropriately decoupled. Typi-

cally, a 0.1 µF capacitor connected near the VCC and

ground pins of the package will provide adequate

decoupling.

Output buffers which drive the specified 4 mA loads

under worst-case conditions may drive 25 to 30 times

this amount under best-case process conditions. Noise

can be reduced by minimizing external load capaci-

tance and reducing simultaneous output transitions in

the same direction. It may also be beneficial to locate

heavily loaded output buffers near the ground pads.

The IOB output buffers have a slew-limited mode which

should be used where output rise and fall times are not

speed critical.

Slew-limited outputs maintain their dc drive capability

but generate less external reflections and internal

noise. More than 32 fast outputs should not be switch-

ing in the same direction simultaneously.

GND

GROUND AND

VCC RING FOR

I/O DRIVERS

VCC

VCC

LOGIC POWER GRID

GND

Figure 31. FPGA Power Distribution

5-3122(F)

32

Lucent Technologies Inc.

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