ATT3042 Ver la hoja de datos (PDF) - Unspecified

Número de pieza

componentes Descripción

Fabricante

ATT3042

Field-Programmable Gate Arrays

Unspecified 

ATT3000 Series Field-Programmable Gate Arrays

Data Sheet

February 1997

Special Configuration Functions

(continued)

Reprogram

The FPGA configuration memory can be rewritten

while the device is operating in the user’s system. To

initiate a reprogramming cycle, the dual-function pack-

age pin DONE/PROG must be given a high-to-low tran-

sition. To reduce sensitivity to noise, the input signal is

filtered for two cycles of the FPGA’s internal timing gen-

erator. When reprogram begins, the user-programma-

ble I/O output buffers are disabled and high-impedance

pull-ups are provided for the package pins. The device

returns to the clear state and clears the configuration

memory before it prompts INITIALIZED. Since this

clear operation uses chip-individual internal timing, the

master might complete the clear operation and then

start configuration before the slave has completed the

clear operation. To avoid this, wire-AND the slave INIT

pins and use them to force a RESET on the master (see

Figure 25). Reprogram control is often implemented by

using an external open-collector driver which pulls

DONE/PROG low. Once it recognizes a stable request,

the FPGA will hold a low until the new configuration has

been completed. Even if the reprogram request is

externally held low beyond the configuration period, the

FPGA will begin operation upon completion of configu-

ration.

DONE Pull-Up

DONE Timing

The timing of the DONE status signal can be controlled

by a selection in the bit stream generation program to

occur a CCLK cycle before, or after, the timing of out-

puts being activated (see Figure 20). This facilitates

control of external functions, such as a PROM enable

or holding a system in a wait-state.

RESET Timing

As with DONE timing, the timing of the release of the

internal RESET can be controlled by a selection in the

bit stream generation program to occur a CCLK cycle

before, or after, the timing of outputs being enabled

(see Figure 20). This reset maintains all user-program-

mable flip-flops and latches in a zero state during con-

figuration.

Crystal Oscillator Division

A selection in the bit stream generation program allows

the user to incorporate a dedicated divide-by-two flip-

flop in the crystal oscillator function. This provides

higher assurance of a symmetrical timing signal.

Although the frequency stability of crystal oscillators is

high, the symmetry of the waveform can be affected by

bias or feedback drive.

DONE/PROG is an open-drain I/O pin that indicates the

FPGA is in the operational state. An optional internal

pull-up resistor can be enabled by the user of the devel-

opment system when the bit stream generation pro-

gram is executed. The DONE/PROG pins of multiple

FPGAs in a daisy chain may be connected together to

indicate that all are DONE or to direct them all to repro-

gram.

28

Lucent Technologies Inc.

Share Link: