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ATT3042

Field-Programmable Gate Arrays

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ATT3000 Series Field-Programmable Gate Arrays

Data Sheet

February 1997

Configuration Modes

Master Mode

In master mode, the FPGA automatically loads configu-

ration data from an external memory device. There are

three master modes which use the internal timing

source to supply the configuration clock (CCLK) to time

the incoming data. Serial master mode uses serial con-

figuration data supplied to data-in (DIN) from a syn-

chronous serial source such as the serial configuration

PROM shown in Figure 21. Parallel master low and

master high modes automatically use parallel data sup-

plied to the D[7:0] pins in response to the 16-bit

address generated by the FPGA. Figure 22 shows an

example of the parallel master mode connections

required. The FPGA HEX starting address is 0000 and

increments for master low mode, and it is FFFF and

decrements for master high mode. These two modes

provide address compatibility with microprocessors

which begin execution from opposite ends of memory.

For master high or low, data bytes are read in parallel

by each read clock (RCLK) and internally serialized by

the configuration clock. As each data byte is read, the

least significant bit of the next byte, D0, becomes the

next bit in the internal serial configuration word. One

master mode FPGA can be used to interface the

configuration program-store, and pass additional

concatenated configuration data to additional FPGAs in

a serial daisy-chain fashion. CCLK is provided for the

slaved devices, and their serialized data is supplied

from DOUT to DIN, DOUT to DIN, etc.

DURING CONFIGURATION

THE 5 kΩ M2 PULL-DOWN

RESISTOR OVERCOMES THE

INTERNAL PULL-UP,

BUT IT ALLOWS M2 TO

BE USER I/O.

GENERAL-

PURPOSE

USER I/O

PINS

SYSTEM RESET

+5 V

M0 M1 PWRDWN

DOUT

M2

HDC

LDC

OTHER

I/O PINS

ATT3000

SERIES

FPGA

RESET

DIN

CCLK

D/P

INIT

*

*

OPTIONAL

IDENTICAL SLAVE

FPGAs CONFIGURED

THE SAME

ATT1700A

DATA

CLK

CE

OE/RESET

CEO

DATA

CLK

CASCADED

ATT1700A

MEMORY

CE

OE/RESET

(HIGH RESETS THE ADDRESS POINTER)

5-3112(C)

Note: The serial configuration PROM supports automatic loading of configuration programs up to 36/64/128 Kbits. Multiple devices can be

cascaded to support additional FPGAs. An early DONE inhibits the data output one CCLK cycle before the FPGA I/O becomes active.

Figure 21. Master Serial Mode

22

Lucent Technologies Inc.

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