AS4LC4M4883C Ver la hoja de datos (PDF) - Austin Semiconductor
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AS4LC4M4883C Datasheet PDF : 20 Pages
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AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C
4 MEG x 4 DRAM
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
NOTE:
tRWC
tRAS
tRP
RAS
V
V
IH
IL
tCSH
tRSH
tCRP
tRCD
tCAS
CAS
V IH
V IL
,,,,,,, ,,,,, ,,,, , ADDR
V
V
IH
IL
, ,,, , ,,,,,, , WE
V
V
IH
IL
, , , DQ VVIIOOHL
,,,,,,,,,,,,,, ,,,,,,,,,, OE
V
V
IH
IL
tASR
tAR
tRAD
tRAH
ROW
tWRP tWRH
NOTE 1
tASC
tRAL
tCAH
COLUMN
tRCS
tRWD
tCWD
tAWD
tACH
tCWL
tRWL
tWP
t CLZ
OPEN
tAA
tRAC
tCAC
tDS
tDH
VALID D OUT
VALID D IN
tOE
tOD
tOEH
ROW
OPEN
DON’T CARE
UNDEFINED
1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement
?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
SYM
tAA
tACH
tAR
tASC
tASR
tAWD
tCAC
tCAH
tCAS
tCLZ
tCRP
tCSH
tCWD
tCWL
tDH
tDS
tOD
-6
MIN MAX
30
15
45
0
0
55
15
10
12 10,000
0
5
50
35
15
10
0
0
15
-7
MIN MAX
35
15
55
0
0
65
20
15
15 10,000
0
5
55
40
15
12
0
0 15
-8
MIN MAX
40
20
60
0
0
65
20
15
20 10,000
0
5
60
45
20
15
0
0
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-6
SYM
tOE
tOEH
tRAC
tRAD
tRAH
tRAL
tRAS
tRCD
tRCS
tRP
tRSH
tRWC
tRWD
tRWL
tWP
tWRH
tWRP
MIN
10
15
10
30
60
16
0
40
13
150
80
15
10
10
10
MAX
15
60
30
10,000
45
-7
MIN MAX
20
12
70
15 35
10
35
70 10,000
16 50
0
50
15
180
90
15
12
10
10
-8
MIN MAX
20
15
80
15 40
10
40
80 10,000
20 60
0
60
15
200
105
20
15
10
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AS4LC4M4
Rev. 11/97
DS000022
2-83
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
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