ADSP-2186L1111 Ver la hoja de datos (PDF) - Analog Devices
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ADSP-2186L1111 Datasheet PDF : 36 Pages
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ADSP-2186L
SYSTEM INTERFACE
Figure 2 shows typical basic system configurations with the
ADSP-2186L, two serial devices, a byte-wide EPROM and
optional external program and data overlay memories (mode
selectable). Programmable wait state generation allows the pro-
cessor to connect easily to slow peripheral devices. The ADSP-
2186L also provides four external interrupts and two serial ports
or six external interrupts and one serial port. Host Memory
Mode allows access to the full external data bus, but limits
addressing to a single address bit (A0). Additional system
peripherals can be added in this mode through the use of exter-
nal hardware to generate and latch address signals.
1/2x CLOCK
OR
CRYSTAL
SERIAL
DEVICE
SERIAL
DEVICE
FULL MEMORY MODE
ADSP-2186L
CLKIN
XTAL
14
ADDR13–0
FL0–2
PF 3
IRQ2/PF 7
IRQE/PF 4
IRQL0/PF 5
IRQL1/PF 6
24
DATA23–0
BMS
WR
MODE C/PF 2
MODE B/PF 1
MODE A/PF 0
RD
IOMS
SPORT1
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SPORT0
SCLK0
RFS0
TFS0
DT0
DR0
PMS
DMS
CMS
BR
BG
BGH
PWD
PWDACK
A13–0
D23–16
D15–8
A0–A21
DATA
BYTE
MEMORY
CS
A10–0
D23–8
A13–0
D23–0
ADDR
I/O SPACE
DATA (PERIPHERALS)
CS 2048 LOCATIONS
ADDR
DATA
OVERLAY
MEMORY
TWO 8K
PM SEGMENTS
TWO 8K
DM SEGMENTS
Clock Signals
The ADSP-2186L can be clocked by either a crystal or a
TTL-compatible clock signal.
The CLKIN input cannot be halted, changed during operation
or operated below the specified frequency during normal operation.
The only exception is while the processor is in the power-down
state. For additional information on the power-down feature,
refer to the ADSP-218x DSP Hardware Reference.
If an external clock is used, it should be a TTL-compatible
signal running at half the instruction rate. The signal is con-
nected to the processor’s CLKIN input. When an external clock
is used, the XTAL input must be left unconnected.
The ADSP-2186L uses an input clock with a frequency equal to
half the instruction rate; a 0.20 MHz input clock yields a 25 ns
processor cycle (which is equivalent to 40 MHz). Normally,
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
Because the ADSP-2186L includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors con-
nected as shown in Figure 3. Capacitor values are dependent on
crystal type and should be specified by the crystal manufacturer.
A parallel-resonant, fundamental frequency, microprocessor-
grade crystal should be used.
A clock output (CLKOUT) signal is generated by the proces-
sor at the processor’s cycle rate. This can be enabled and
disabled by the CLKODIS bit in the SPORT0 Autobuffer
Control Register.
1/2x CLOCK
OR
CRYSTAL
SERIAL
DEVICE
SERIAL
DEVICE
SYSTEM
INTERFACE
OR
CONTROLLER
16
HOST MEMORY MODE
ADSP-2186L
CLKIN
XTAL
1
A0
FL0–2
PF 3
IRQ2/PF 7
IRQE/PF 4
IRQL0/PF 5
IRQL1/PF 6
16
DATA23–8
BMS
MODE C/PF 2
WR
MODE B/PF 1
MODE A/PF 0
RD
SPORT1
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SPORT0
SCLK0
RFS0
TFS0
DT0
DR0
IOMS
PMS
DMS
CMS
BR
BG
BGH
IDMA PORT
IRD/D6
IWR/D7
IS/D4
IAL/D5
IACK/D3
IAD15–0
PWD
PWDACK
Figure 2. Basic System Configuration
CLKIN
XTAL
DSP
CLKOUT
Figure 3. External Crystal Connections
Reset
The RESET signal initiates a master reset of the ADSP-2186L.
The RESET signal must be asserted during the power-up
sequence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is
applied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the mini-
mum pulsewidth specification, tRSP.
The RESET input contains some hysteresis; however, if an RC
circuit is used to generate the RESET signal, an external Schmidt
trigger is recommended.
REV. B
–7–
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