ADSP-2186L1111 Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

ADSP-2186L1111

DSP Microcomputer

Analog Devices 

ADSP-2186L

Interrupt routines can either be nested, with higher priority

interrupts taking precedence, or processed sequentially. Inter-

rupts can be masked or unmasked with the IMASK register.

Individual interrupt requests are logically ANDed with the bits

in IMASK; the highest priority unmasked interrupt is then

selected. The power-down interrupt is nonmaskable.

The ADSP-2186L masks all interrupts for one instruction cycle

following the execution of an instruction that modifies the

IMASK register. This does not affect serial port autobuffering

or DMA transfers.

The interrupt control register, ICNTL, controls interrupt nest-

ing and defines the IRQ0, IRQ1 and IRQ2 external interrupts to

be either edge- or level-sensitive. The IRQE pin is an external

edge-sensitive interrupt and can be forced and cleared. The

IRQL0 and IRQL1 pins are external level-sensitive interrupts.

The IFC register is a write-only register used to force and clear

interrupts.

On-chip stacks preserve the processor status and are automati-

cally maintained during interrupt handling. The stacks are twelve

levels deep to allow interrupt, loop and subroutine nesting.

The following instructions allow global enable or disable servic-

ing of the interrupts (including power-down), regardless of the

state of IMASK. Disabling the interrupts does not affect serial

port autobuffering or DMA.

ENA INTS;

DIS INTS;

When the processor is reset, interrupt servicing is enabled.

LOW POWER OPERATION

The ADSP-2186L has three low power modes that significantly

reduce the power dissipation when the device operates under

standby conditions. These modes are:

• Power-Down

• Idle

• Slow Idle

The CLKOUT pin may also be disabled to reduce external

power dissipation.

Power-Down

The ADSP-2186L processor has a low power feature that lets

the processor enter a very low power dormant state through

hardware or software control. Following is a brief list of power-

down features. Refer to the ADSP-218x DSP Hardware Reference,

“System Interface” chapter, for detailed information about the

power-down feature.

• Quick recovery from power-down. The processor begins

executing instructions in as few as 400 CLKIN cycles.

• Support for an externally generated TTL or CMOS proces-

sor clock. The external clock can continue running during

power-down without affecting the lowest power rating and

400 CLKIN cycle recovery.

• Support for crystal operation includes disabling the oscillator

to save power (the processor automatically waits approxi-

mately 4096 CLKIN cycles for the crystal oscillator to start

or stabilize), and letting the oscillator run to allow 400 CLKIN

cycle start-up.

• Power-down is initiated by either the power-down pin (PWD)

or the software power-down force bit.

• Interrupt support allows an unlimited number of instructions

to be executed before optionally powering down. The power-

down interrupt also can be used as a nonmaskable, edge-

sensitive interrupt.

• Context clear/save control allows the processor to continue

where it left off or start with a clean context when leaving the

power-down state.

• The RESET pin also can be used to terminate power-down.

• Power-down acknowledge (PWDACK) pin indicates when

the processor has entered power-down.

Idle

When the ADSP-2186L is in the Idle Mode, the processor waits

indefinitely in a low power state until an interrupt occurs. When

an unmasked interrupt occurs, it is serviced; execution then con-

tinues with the instruction following the IDLE instruction. In Idle

mode IDMA, BDMA and autobuffer cycle steals still occur.

Slow Idle

The IDLE instruction is enhanced on the ADSP-2186L to let

the processor’s internal clock signal be slowed, further reducing

power consumption. The reduced clock frequency, a program-

mable fraction of the normal clock rate, is specified by a select-

able divisor given in the IDLE instruction. The format of the

instruction is:

IDLE (n)

where n = 16, 32, 64 or 128. This instruction keeps the proces-

sor fully functional, but operating at the slower clock rate. While

it is in this state, the processor’s other internal clock signals such

as SCLK, CLKOUT and timer clock, are reduced by the same

ratio. The default form of the instruction, when no clock divisor

is given, is the standard IDLE instruction.

When the IDLE (n) instruction is used, it effectively slows down

the processor’s internal clock and thus its response time to incom-

ing interrupts. The one-cycle response time of the standard idle

state is increased by n, the clock divisor. When an enabled inter-

rupt is received, the ADSP-2186L will remain in the idle state

for up to a maximum of n processor cycles (n = 16, 32, 64 or

128) before resuming normal operation.

When the IDLE (n) instruction is used in systems that have an

externally generated serial clock (SCLK), the serial clock rate

may be faster than the processor’s reduced internal clock rate.

Under these conditions, interrupts must not be generated at a

faster rate than can be serviced due to the additional time the

processor takes to come out of the idle state (a maximum of n

processor cycles).

–6–

REV. B

Share Link: