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ADSP-2186L1111

DSP Microcomputer

Analog Devices 

ADSP-2186L

Table V. BDMA Data Formats

BTYPE

00

01

10

11

Internal

Memory Space

Program Memory

Data Memory

Data Memory

Data Memory

Word Size

24

16

8

8

Alignment

Full Word

Full Word

MSBs

LSBs

Unused bits in the 8-bit data memory formats are filled with 0s.

The BIAD register field is used to specify the starting address for

the on-chip memory involved with the transfer. The 14-bit BEAD

register specifies the starting address for the external byte memory

space. The 8-bit BMPAGE register specifies the starting page for

the external byte memory space. The BDIR register field selects

the direction of the transfer. Finally the 14-bit BWCOUNT

register specifies the number of DSP words to transfer and

initiates the BDMA circuit transfers.

BDMA accesses can cross page boundaries during sequential

addressing. A BDMA interrupt is generated on the completion

of the number of transfers specified by the BWCOUNT register.

The BWCOUNT register is updated after each transfer so it can

be used to check the status of the transfers. When it reaches

zero, the transfers have finished and a BDMA interrupt is gener-

ated. The BMPAGE and BEAD registers must not be accessed

by the DSP during BDMA operations.

The source or destination of a BDMA transfer will always be

on-chip program or data memory, regardless of the values of

Mode B, PMOVLAY or DMOVLAY.

When the BWCOUNT register is written with a nonzero value,

the BDMA circuit starts executing byte memory accesses with

wait states set by BMWAIT. These accesses continue until the

count reaches zero. When enough accesses have occurred to

create a destination word, it is transferred to or from on-chip

memory. The transfer takes one DSP cycle. DSP accesses to

external memory have priority over BDMA byte memory accesses.

The BDMA Context Reset bit (BCR) controls whether the

processor is held off while the BDMA accesses are occurring.

Setting the BCR bit to 0 allows the processor to continue opera-

tions. Setting the BCR bit to 1 causes the processor to stop

execution while the BDMA accesses are occurring, to clear the

context of the processor and start execution at address 0 when

the BDMA accesses have completed.

Internal Memory DMA Port (IDMA Port; Host Memory Mode)

The IDMA Port provides an efficient means of communication

between a host system and the ADSP-2186L. The port is used

to access the on-chip program memory and data memory of the

DSP with only one DSP cycle per word overhead. The IDMA

port cannot, however, be used to write directly to the DSP’s

memory-mapped control registers.

The IDMA port has a 16-bit multiplexed address and data bus

and supports 24-bit program memory. The IDMA port is com-

pletely asynchronous and can be written to while the ADSP-

2186L is operating at full speed.

The DSP memory address is latched and then automatically incre-

mented after each IDMA transaction. An external device can

therefore access a block of sequentially addressed memory by

specifying only the starting address of the block. This increases

throughput as the address does not have to be sent for each

memory access.

IDMA Port access occurs in two phases. The first is the IDMA

Address Latch cycle. When the acknowledge is asserted, a 14-bit

address and 1-bit destination type can be driven onto the bus by

an external device. The address specifies an on-chip memory

location, the destination type specifies whether it is a DM or

PM access. The falling edge of the address latch signal latches

this value into the IDMAA register.

Once the address is stored, data can then either be read from or

written to the ADSP-2186L’s on-chip memory. Asserting the

select line (IS) and the appropriate read or write line (IRD and

IWR respectively) signals the ADSP-2186L that a particular

transaction is required. In either case, there is a one-processor-

cycle delay for synchronization. The memory access consumes

one additional processor cycle.

Once an access has occurred, the latched address is automati-

cally incremented and another access can occur.

Through the IDMAA register, the DSP can also specify the

starting address and data format for DMA operation.

Bootstrap Loading (Booting)

The ADSP-2186L has two mechanisms to allow automatic

loading of the internal program memory after reset. The method

for booting is controlled by the Mode A, B and C configuration

bits as shown in Table VI. These four states can be compressed

into two-state bits by allowing an IDMA boot with Mode C = 1.

However, three bits are used to ensure future compatibility with

parts containing internal program memory ROM.

BDMA Booting

When the MODE pins specify BDMA booting, the ADSP-2186L

initiates a BDMA boot sequence when RESET is released.

The BDMA interface is set up during reset to the following

defaults when BDMA booting is specified: the BDIR, BMPAGE,

BIAD and BEAD registers are set to 0; the BTYPE register is

set to 0 to specify program memory 24-bit words; and the

BWCOUNT register is set to 32. This causes 32 words of on-chip

program memory to be loaded from byte memory. These 32

words are used to set up the BDMA to load in the remaining

program code. The BCR bit is also set to 1, which causes program

execution to be held off until all 32 words are loaded into on-chip

program memory. Execution then begins at address 0.

The ADSP-2100 Family development software (Revision 5.02

and later) fully supports the BDMA booting feature and can

generate byte memory space compatible boot code.

The IDLE instruction can also be used to allow the processor to

hold off execution while booting continues through the BDMA

interface. For BDMA accesses while in Host Mode, the addresses

to boot memory must be constructed externally to the ADSP-

2186L. The only memory address bit provided by the processor

is A0.

–10–

REV. B

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