ADP3110AKRZ Ver la hoja de datos (PDF) - ON Semiconductor
Número de pieza
componentes Descripción
Fabricante
ADP3110AKRZ Datasheet PDF : 8 Pages
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OD 3
IN 2
VCC
TSD
UVLO
START STOP
MIN DRVL
OFF TIMER
ADP3110A
FALLING
EDGE
DELAY
FALLING
EDGE
DELAY
NON−OVERLAP
TIMERS
MONITOR
MONITOR
Figure 1. Block Diagram
1 BST
8 DRVH
7 SWN
4 VCC
5 DRVL
6 PGND
PIN DESCRIPTION
SO−8 DFN8 Symbol
1
1
BST
2
2
IN
3
3
OD
4
4
VCC
5
5
DRVL
6
6
PGND
7
7
SWN
8
8
DRVH
Description
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds
this bootstrap voltage for the high−side MOSFET as it is switched. The recommended capacitor value
is between 100 nF and 1.0 mF. An external diode is required with the ADP3110A.
Logic−Level Input. This pin has primary control of the drive outputs.
Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low.
Input Supply. A 1.0 mF ceramic capacitor should be connected from this pin to PGND.
Output drive for the lower MOSFET.
Power Ground. Should be closely connected to the source of the lower MOSFET.
Switch Node. Connect to the source of the upper MOSFET.
Output drive for the upper MOSFET.
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