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ADMC300 Datasheet PDF : 42 Pages
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ADMC300
PIN FUNCTION DESCRIPTION
The ADMC300 is available in an 80-lead TQFP package. Table I
contains the pin descriptions.
Pin
Group
Name
RESET
SPORT0
SPORT1
Table I. Pin List
#
of Input/
Pins Output Function
1I
5 I/O
6 I/O
Processor Reset Input.
Serial Port 0 Pins (TFS0, RFS0,
DT0, DR0, SCLK0).
Serial Port 1 Pins (TFS1,
RFS1, DT1, DR1A, DR1B,
SCLK1).
Memory Map
The ADMC300 has two distinct memory types; program
memory and data memory. In general, program memory con-
tains user code and coefficients, while the data memory is used
to store variables and data during program execution. Both pro-
gram memory RAM and ROM is provided on the ADMC300.
Program memory RAM is arranged in two noncontiguous 2K ×
24-bit blocks, one starting at address 0x0000 and the other at
0x1800. Program memory ROM is located at address 0x0800.
Data memory is arranged as a 1K × 16-bit block starting at
address 0x3800. The motor control peripherals are memory
mapped into a region of the data memory space starting at
0x2000. The complete program and data memory maps are
given in Tables II and III respectively.
Table II. Program Memory Map
CLKOUT
1O
CLKIN, XTAL 2 I, O
PIO0–PIO11 12 I/O
AUX0–AUX1 2 O
AH–CL
PWMTRIP
6O
1I
PWMPOL
1I
PWMSYNC 1 O
V1–V5
5I
Processor Clock Output.
External Clock or Quartz Crystal
Connection Point.
Digital I/O Port, External Con-
vert Start and Event Timer
Pins.
Auxiliary PWM Outputs.
PWM Outputs.
PWM Trip Signal.
PWM Polarity Pin.
PWM Synchronization Pin.
Noninverting Inputs of the Dif-
ferential ADCs’ Input Amplifiers.
Address Range
0x0000–0x005F
0x0060–0x071F
0x0720–0x07DF
0x07E0–0x07FF
0x0800–0x0E20
0xE21–0xFD6
0xFD7–0x0FFF
0x1000–0x17FF
0x1800–0x1FFF
0x2000–0x3FFF
Memory
Type
RAM
RAM
RAM
RAM
ROM
ROM
ROM
RAM
Function
Interrupt Vector Table
User Program Space
Reserved by Debugger
Reserved by Monitor
ROM Monitor
ROM Math and Motor
Control Utilities
Reserved
Unused
User Program Space
Unused
V1N–V5N
5I
Inverting Inputs of the Differen-
tial ADCs’ Input Amplifiers.
Table III. Data Memory Map
REFINA–
REFINB
2I
Voltage reference inputs for
ADCs.
Address Range
Memory
Type
Function
VREF
1O
MUX0–MUX2 3 O
EIA, EIB, EIZP 3 I
AVDD
4
AGND
4
VDD
6
GND
9
Voltage Reference Output.
Multiplexer Control Lines.
Encoder Interface Pins.
Analog Power Supply.
Analog Ground.
Digital Power Supply.
Digital Ground.
INTERRUPT OVERVIEW
The ADMC300 can respond to nineteen different interrupt
sources, eight of which are internal DSP core interrupts and
eleven interrupts from the motor control peripherals. The eight
DSP core interrupts comprise the peripheral (IRQ2), SPORT0
receive, SPORT0 transmit, SPORT1 receive (or IRQ0), SPORT1
transmit (or IRQ1), two software and the interval timer interrupts.
In addition, the motor control peripherals add eleven interrupts
that include two ADC, two PWM, five peripheral I/O, one en-
coder interface and one event timer interrupt. The interrupts are
internally prioritized and individually maskable. All peripheral
interrupts are multiplexed into the DSP core through the pe-
ripheral IRQ2 interrupt. The programmable interrupt controller
manages the masking and vector addressing of all eleven periph-
eral interrupts. A detailed description of the operation of the
entire interrupt system of the ADMC300 is given later, after a
more detailed description of the various peripheral systems.
Windows is a registered trademark of Microsoft Corporation.
0x0000–0x1FFF
0x2000–0x20FF
0x2100–0x37FF
0x3800–0x3B5F
0x3B60–0x3BFF
0x3C00–0x3FFF
RAM
RAM
Unused
Memory Mapped Registers
Unused
User Data Space
Reserved by Monitor
Memory Mapped Registers
ROM Code
The 2K × 24-bit block of program memory ROM starting at ad-
dress 0x0800 contains a monitor function that is used to download
and execute user programs via the serial port. In addition, the
monitor function supports an interactive mode in which com-
mands are received and processed from a host. An example of such
a host is the Windows®-based Motion Control Debugger that is
part of the software development system for the ADMC300. In
the interactive mode, the host can access both the internal DSP
and peripheral motor control registers of the ADMC300, read and
write to both program and data memory, implement breakpoints
and perform single-step and run/halt operation as part of the pro-
gram debugging cycle.
In addition to the monitor function, the program memory ROM
contains a number of useful mathematical and motor control util-
ities that can be called as subroutines from the user code. A com-
plete list of these ROM functions is given in Table IV. The start
address of the function in the program memory ROM is also given.
Refer to the ADMC300 DSP Motor Controller Developer’s Reference
Manual for more details of the ROM functions.
–10–
REV. B
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