ADG786BCP Ver la hoja de datos (PDF) - Analog Devices

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Fabricante

ADG786BCP

2.5 Ω
, 1.8 V to 5.5 V, ±2.5 V Triple/Quad SPDT Switches in Chip Scale Packages

Analog Devices 

ADG786/ADG788

Table I. ADG786 Truth Table

A2 A1 A0 EN ON Switch

X

X

X

1

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

0

1

1

1

0

None

D1-S1A, D2-S2A, D3-S3A

D1-S1B, D2-S2A, D3-S3A

D1-S1A, D2-S2B, D3-S3A

D1-S1B, D2-S2B, D3-S3A

D1-S1A, D2-S2A, D3-S3B

D1-S1B, D2-S2A, D3-S3B

D1-S1A, D2-S2B, D3-S3B

D1-S1B, D2-S2B, D3-S3B

Table II. ADG788 Truth Table

Logic

0

1

Switch A

OFF

ON

Switch B

ON

OFF

VDD

VSS

IDD

ISS

GND

S

D

IN

VD (VS)

RON

∆RON

RFLAT(ON)

IS (OFF)

ID, IS (ON)

VINL

VINH

IINL(IINH)

CS (OFF)

CD, CS(ON)

CIN

tON

tOFF

tON(EN)

tOFF(EN)

tOPEN

Charge

Off Isolation

Crosstalk

On Response

Insertion Loss

TERMINOLOGY

Most Positive Power Supply Potential

Most Negative Power Supply in a Dual Supply Application. In single supply applications, this should be tied to

ground close to the device.

Positive Supply Current

Negative Supply Current

Ground (0 V) Reference

Source Terminal. May be an input or output

Drain Terminal. May be an input or output

Logic Control Input

Analog Voltage on Terminals D, S

Ohmic Resistance between D and S

On Resistance Match between Any Two Channels, i.e., RONmax – RONmin.

Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured

over the specified analog signal range.

Source Leakage Current with the Switch “OFF”

Channel Leakage Current with the Switch “ON”

Maximum Input Voltage for Logic “0”

Minimum Input Voltage for Logic “1”

Input Current of the Digital Input

“OFF” Switch Source Capacitance. Measured with reference to ground.

“ON” Switch Capacitance. Measured with reference to ground.

Digital Input Capacitance

Delay time measured between the 50% and 90% points of the digital inputs and the switch “ON” condition.

Delay time measured between the 50% and 90% points of the digital input and the switch “OFF” condition.

Delay time between the 50% and 90% points of the EN digital input and the switch “ON” condition.

Delay time between the 50% and 90% points of the EN digital input and the switch “OFF” condition.

“OFF” time measured between the 80% points of both switches when switching from one address state to another.

A measure of the glitch impulse transferred Injection from the digital input to the analog output during switching.

A measure of unwanted signal coupling through an “OFF” switch.

A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic

capacitance.

The Frequency Response of the “ON” Switch

The Loss Due to the ON Resistance of the Switch.

–6–

REV. 0

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