ADG752BRM Ver la hoja de datos (PDF) - Analog Devices

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componentes Descripción

Fabricante

ADG752BRM

CMOS, Low Voltage RF/Video, SPDT Switch

Analog Devices 

ADG752–SPECIFICATIONS (VDD = +5 V ؎ 10%, GND = 0 V, unless otherwise noted.)

Parameter

B Version

–40؇C

+25؇C

to +85؇C

Units

Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range

On-Resistance (RON)

On-Resistance Match Between

Channels (∆RON)

On-Resistance Flatness (RFLAT(ON))

LEAKAGE CURRENTS

Source OFF Leakage IS (OFF)

Channel ON Leakage ID, IS (ON)

15

18

0.1

0.6

2

± 0.01

± 0.25

± 0.01

± 0.25

0 V to VDD

20

0.6

3

± 3.0

± 3.0

V

Ω typ

Ω max

Ω typ

Ω max

Ω typ

Ω max

nA typ

nA max

nA typ

nA max

VS = 0 V to VDD, IDS = 10 mA;

Test Circuit 1

VS = 0 V to VDD, IDS = 10 mA

VS = 0 V to 2.5 V, IDS = 10 mA

VDD = + 4.5 V

VD = 4.5 V/1 V, VS = 1 V/4.5 V;

Test Circuit 2

VD = VS = 1 V, or 4.5 V;

Test Circuit 3

DIGITAL INPUTS

Input High Voltage, VINH

Input Low Voltage, VINL

Input Current

IINL or IINH

CIN, Digital Input Capacitance

DYNAMIC CHARACTERISTICS1

tON

tOFF

Break-Before-Make Time Delay

Off Isolation

Crosstalk

–3 dB Bandwidth

CS (OFF)

CD, CS (ON)

POWER REQUIREMENTS

IDD

2.4

0.8

0.001

± 0.5

2

8

13

3

5

6

1

–80

–80

250

4

15

0.001

0.1

0.5

V min

V max

µA typ

µA max

pF typ

ns typ

ns max

ns typ

ns max

ns typ

ns min

dB typ

dB typ

MHz typ

pF typ

pF typ

µA typ

µA max

VIN = VINL or VINH

RL = 300 Ω, CL = 35 pF;

VS = 3 V, Test Circuit 4

RL = 300 Ω, CL = 35 pF;

VS = 3 V, Test Circuit 4

RL = 300 Ω, CL = 35 pF;

VS = 3 V, Test Circuit 5

RL = 50 Ω, CL = 5 pF, f = 30 MHz;

Test Circuit 6

RL = 50 Ω, CL = 5 pF, f = 30 MHz;

Test Circuit 7

RL = 50 Ω, CL = 5 pF, Test Circuit 8

VDD = +5.5 V

Digital Inputs = 0 V or +5.5 V

NOTES

1Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

–2–

REV. 0

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