AD9763AST Ver la hoja de datos (PDF) - Analog Devices

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Fabricante

AD9763AST

10-Bit, 125 MSPS Dual TxDAC+® D/A Converter

Analog Devices 

AD9763

DEFINITIONS OF SPECIFICATIONS

Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the

actual analog output from the ideal output, determined by a

straight line drawn from zero to full scale.

Differential Nonlinearity (or DNL)

DNL is the measure of the variation in analog value, normalized

to full scale, associated with a 1 LSB change in digital input

code.

Monotonicity

A D/A converter is monotonic if the output either increases or

remains constant as the digital input increases.

Offset Error

The deviation of the output current from the ideal of zero is

called offset error. For IOUTA, 0 mA output is expected when the

inputs are all 0s. For IOUTB, 0 mA output is expected when all

inputs are set to 1s.

Gain Error

The difference between the actual and ideal output span. The

actual span is determined by the output when all inputs are set

to 1s minus the output when all inputs are set to 0s.

Output Compliance Range

The range of allowable voltage at the output of a current-output

DAC. Operation beyond the maximum compliance limits may

cause either output stage saturation or breakdown resulting in

nonlinear performance.

Temperature Drift

Temperature drift is specified as the maximum change from the

ambient (+25°C) value to the value at either TMIN or TMAX. For

offset and gain drift, the drift is reported in ppm of full-scale

range (FSR) per degree C. For reference drift, the drift is

reported in ppm per degree C.

Power Supply Rejection

The maximum change in the full-scale output as the supplies

are varied from nominal to minimum and maximum specified

voltages.

Settling Time

The time required for the output to reach and remain within a

specified error band about its final value, measured from the

start of the output transition.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired

output transients that are quantified by a glitch impulse. It is

specified as the net area of the glitch in pV-s.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output

signal and the peak spurious signal over the specified bandwidth.

Total Harmonic Distortion

THD is the ratio of the rms sum of the first six harmonic

components to the rms value of the measured input signal. It is

expressed as a percentage or in decibels (dB).

RSET1

2k⍀

0.1␮F

RSET2

2k⍀

FSADJ1

REFIO

FSADJ2

1.2V REF

GAINCTRL

DVDD

DCOM

*RETIMED CLOCK OUTPUT

LECROY 9210

PULSE

GENERATOR

5V

CLK1/IQCLK CLK2/IQRESET

AVDD

PMOS

CURRENT

SOURCE

ARRAY

PMOS

CURRENT

SOURCE

ARRAY

CLK

DIVIDER

DAC 1

LATCH

DAC 2

LATCH

SLEEP

SEGMENTED

SWITCHES FOR

DAC1

LSB

SWITCH

IOUTA1

IOUTB1

SEGMENTED

SWITCHES FOR

DAC2

LSB

SWITCH

IOUTA2

IOUTB2

AD9763

MULTIPLEXING LOGIC

WRT1 /

IQWRT

CHANNEL 1 LATCH

CHANNEL 2 LATCH

MODE

DVDD

ACOM DCOM

50⍀

5V

50⍀

DB0 – DB9

DIGITAL

DATA

TEKTRONIX

AWG-2021

w/OPTION 4

DB0 – DB9

WRT2 /

IQSEL

*AWG2021 CLOCK RETIMED SUCH THAT

DIGITAL DATA TRANSITIONS ON FALLING

EDGE OF 50% DUTY CYCLE CLOCK

MINI

CIRCUITS

T1-1T

50⍀

TO HP3589A

SPECTRUM/

NETWORK

ANALYZER

Figure 2. Basic AC Characterization Test Setup for AD9763, Testing Port 1 in Dual Port Mode, Using Independent

GAINCTRL Resistors on FSADJ1 and FSADJ2

–6–

REV. B

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