AD7841AS Ver la hoja de datos (PDF) - Analog Devices
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AD7841AS Datasheet PDF : 12 Pages
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AD7841
Unipolar Configuration
Figure 11 shows the AD7841 in the unipolar binary circuit
configuration. The VREF(+) input of the DAC is driven by the
AD586, a +5 V reference. VREF(–) is tied to ground. Table II
gives the code table for unipolar operation of the AD7841.
Other suitable references include the REF02, a precision +5 V
reference, and the REF195, a low dropout, micropower preci-
sion +5 V reference.
+15V +5V
2
6
8 AD586
5
C1
1F
4
R1
10k⍀
VDD
VREF(+)
VCC
VOUT
AD7841*
DUTGND
VOUT
(0 TO +10V)
SIGNAL
GND
VREF(–)
GND
VSS
–15V
SIGNAL
GND
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 11. Unipolar +10 V Operation
Offset and gain may be adjusted in Figure 11 as follows: To
adjust offset, disconnect the VREF(–) input from 0 V, load the
DAC with all 0s and adjust the VREF(–) voltage until VOUT = 0 V.
For gain adjustment, the AD7841 should be loaded with all 1s
and R1 adjusted until VOUT = 2 VREF(+) – 1 LSB = 10 V(16383/
16384) = 9.99939 V.
Many circuits will not require these offset and gain adjustments.
In these circuits R1 can be omitted. Pin 5 of the AD586 may be
left open circuit and Pin 2 (VREF(–)) of the AD7841 tied to 0 V.
Table II. Code Table for Unipolar Operation
Binary Number in DAC Register
MSB␣ ␣ ␣ ␣ ␣ ␣ ␣ ␣
LSB
11 1111 1111 1111
10 0000 0000 0000
01 1111 1111 1111
00 0000 0000 0001
00 0000 0000 0000
Analog Output
(VOUT)
2 VREF (16383/16384) V
2 VREF (8192/16384) V
2 VREF (8191/16384) V
2 VREF (1/16384) V
0V
NOTES
VREF = VREF(+); VREF(–) = 0 V for unipolar operation.
For VREF(+) = +5 V, 1 LSB = +10 V/214 = +10 V/16384 = 610 µV.
Bipolar Configuration
Figure 12 shows the AD7841 set up for ± 10 V operation. The
AD588 provides precision ± 5 V tracking outputs that are fed to
the VREF(+) and VREF(–) inputs of the AD7841. The code table
for bipolar operation of the AD7841 is shown in Table III.
In Figure 12, full-scale and bipolar zero adjustments are pro-
vided by varying the gain and balance on the AD588. R2 varies
the gain on the AD588 while R3 adjusts the offset of both the
+5 V and –5 V outputs together with respect to ground.
For bipolar-zero adjustment, the DAC is loaded with
1000␣ .␣ .␣ .␣ 0000 and R3 is adjusted until VOUT = 0 V. Full scale
is adjusted by loading the DAC with all 1s and adjusting R2
until VOUT = 10(8191/8192) V = 9.99878 V.
When bipolar-zero and full-scale adjustment are not needed, R2
and R3 can be omitted. Pin 12 on the AD588 should be con-
nected to Pin 11 and Pin 5 should be left floating.
R1
39k⍀
+15V +5V
R2
100k⍀
7
C1
1F 9
5
10
11
46
2
3
1
AD588
14
15
16
R3
100k⍀
12 8 13
VDD
VREF(+)
VCC
VOUT
AD7841*
DUTGND
VREF(–)
VSS GND
–15V
VOUT
(–10V TO +10V)
SIGNAL
GND
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 12. Bipolar ±10 V Operation
Table III. Code Table for Bipolar Operation
Binary Number in DAC
Register
MSB
LSB
11 1111 1111 1111
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
00 0000 0000 0001
00 0000 0000 0000
Analog Output
(VOUT)
2[VREF(–) + VREF (16383/16384)] V
2[VREF(–) + VREF (8193/16384)] V
2[VREF(–) + VREF (8192/16384)] V
2[VREF(–) + VREF (8191/16384)] V
2[VREF(–) + VREF (1/16384)] V
2[VREF(–)] V
NOTES
VREF = (VREF(+) – VREF(–)).
For VREF(+) = +5 V, and VREF(–) = –5 V, VREF = 10 V, 1 LSB = 2 VREF V/214 =
20 V/16384 = 1.22 mV.
CONTROLLED POWER-ON OF THE OUTPUT STAGE
A block diagram of the output stage of the AD7841 is shown in
Figure 13. It is capable of driving a load of 5 kΩ in parallel with
50 pF. G1 to G6 are transmission gates used to control the
power on voltage present at VOUT. On power up G1 and G2 are
also used in conjunction with the CLR input to set VOUT to the
user defined voltage present at the DUTGND pin. When CLR
is taken back high, the DAC outputs reflect the data in the DAC
registers.
G1
DAC
G6
G3
VOUT
G2
G4
R = 60k⍀
R
G5 14k⍀
DUTGND
Figure 13. Block Diagram of AD7841 Output Stage
–8–
REV. 0
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