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5962-9063302MCA

Quad Precision, Low Cost, High Speed, BiFET Op Amp

Analog Devices 

AD713

MEASURING AD713 SETTLING TIME

The photos of Figures 2 and 3 show the dynamic response of

the AD713 while operating in the settling time test circuit of

Figure 1. The input of the settling time fixture is driven by a

flat-top pulse generator. The error signal output from the false

summing node of A1, the AD713 under test, is clamped, ampli-

fied by op amp A2 and then clamped again.

The error signal is thus clamped twice: once to prevent overload-

ing amplifier A2 and then a second time to avoid overloading the

oscilloscope preamp. A Tektronix oscilloscope preamp type 7A26

was carefully chosen because it recovers from the approximately

0.4 V overload quickly enough to allow accurate measurement

of the AD713’s 1 µs settling time. Amplifier A2 is a very high

speed FET input op amp; it provides a voltage gain of 10, am-

plifying the error signal output of the AD713 under test (providing

an overall gain of 5).

Figure 1. Settling Time Test Circuit

Figure 3. Settling Characteristics to –10 V Step.

Upper Trace: Output of AD713 Under Test (5 V/div).

Lower Trace: Amplified Error Voltage (0.01%/ div)

POWER SUPPLY BYPASSING

The power supply connections to the AD713 must maintain a

low impedance to ground over a bandwidth of 4 MHz or more.

This is especially important when driving a significant resistive

or capacitive load, since all current delivered to the load comes

from the power supplies. Multiple high quality bypass capacitors

are recommended for each power supply line in any critical

application. A 0.1 µF ceramic and a 1 µF electrolytic capacitor

as shown in Figure 4 placed as close as possible to the amplifier

(with short lead lengths to power supply common) will assure

adequate high frequency bypassing in most applications. A

minimum bypass capacitance of 0.1 µF should be used for any

application.

Figure 2. Settling Characteristics 0 V to +10 V Step.

Upper Trace: Output of AD713 Under Test (5 V/div).

Lower Trace: Amplified Error Voltage (0.01%/div)

Figure 4. Recommended Power Supply Bypassing

REV. C

–7–

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