AD6644PCB Ver la hoja de datos (PDF) - Analog Devices
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AD6644PCB Datasheet PDF : 19 Pages
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AD6644–SPECIFICATIONS
Parameter
DATA READY (DRY5)/DATA, OVR
Data Ready to DATA Delay (Hold Time)2
Encode = 65 MSPS (50% Duty Cycle)
Encode = 40 MSPS (50% Duty Cycle)
Data Ready to DATA Delay (Setup Time)2
@ 65 MSPS (50% Duty Cycle)
@ 40 MSPS (50% Duty Cycle)
Name
tH_DR
tS_DR
Temp
Full
Full
Full
Full
Test
Level
IV
IV
IV
IV
AD6644AST-40/65
Min
Typ
Max
Note 6
8.0
8.6
9.4
12.8
13.4
14.2
Note 6
3.2
5.5
6.5
8.0
10.3
11.3
Unit
ns
ns
ns
ns
APERTURE DELAY
tA
25°C
V
100
ps
APERTURE UNCERTAINTY (JITTER)
tJ
25°C
V
0.2
ps rms
NOTES
1Several timing parameters are a function of tENC and tENCH.
2To compensate for a change in duty cycle for tH_DR and tS_DR use the following equation:
NewtH_DR = (tH_DR – % Change(tENCH)) × tENC/2
NewtS_DR = (tS_DR – % Change(tENCH)) × tENC/2.
3ENCODE to DATA Delay (Hold Time) is the absolute minimum propagation delay through the analog-to-digital converter.
4ENCODE to DATA Delay (Setup Time) is calculated relative to 65 MSPS (50% duty cycle). In order to calculate t S_E for a given encode use the following equation:
NewtS_E = tENC(NEW) – tENC + tS_E (i.e., for 40 MSPS: NewtS_E(TYP) = 25 × 10–9 – 15.38 × 10–9 + 9.8 × 10–9 = 19.4 × 10 –9).
5DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY.
6Data Ready to DATA Delay(tH_DR and tS_DR) is calculated relative to 65 MSPS (50% duty cycle) and is dependent on tENC and duty cycle. In order to calculate tH_DR
and tS_DR for a given encode use the following equations:
NewtH_DR = tENC(NEW)/2 – tENCH + tH_DR (i.e., for 40 MSPS: NewtH_DR(TYP) = 12.5 × 10–9 – 7.69 × 10–9 + 8.6 × 10–9 = 13.4 × 10–9
NewtS_DR = tENC(NEW)/2 – tENCH + tS_DR (i.e., for 40 MSPS: NewtS_DR(TYP) = 12.5 × 10–9 – 7.69 × 10–9 + 5.5 × 10–9 = 10.3 × 10–9.
Specifications subject to change without notice.
tA
N
AIN
N؉1
N؉2
N؉3
tENC
ENC, ENC
D[13:0], OVR
N
tE_FL
tE_RL
DRY
tENCH
N؉1
N–3
tENCL
N؉2
tE_DR
N؉3
N–2
tDR
N–1
tS_DR
tH_DR
Figure 1. Timing Diagram
N؉4
tS_E
N؉4
tH_E
N
–4–
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