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AD6644PCB Ver la hoja de datos (PDF) - Analog Devices

Número de pieza
componentes Descripción
Fabricante
AD6644PCB
ADI
Analog Devices ADI
AD6644PCB Datasheet PDF : 19 Pages
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AD6644
AC SPECIFICATIONS1(AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = Maximum Conversion Rate MSPS; TMIN = –25؇C, TMAX = +85؇C)
Parameter
SNR
Analog Input
@ –1 dBFS
2.2 MHz
15.5 MHz
30.5 MHz
SINAD2
Analog Input
@ –1 dBFS
2.2 MHz
15.5 MHz
30.5 MHz
WORST HARMONIC (2ND or 3RD)2
Analog Input 2.2 MHz
@ –1 dBFS
15.5 MHz
30.5 MHz
WORST HARMONIC (4TH or Higher)2
Analog Input 2.2 MHz
@ –1 dBFS
15.5 MHz
30.5 MHz
TWO-TONE SFDR2, 3, 4
TWO-TONE IMD REJECTION2, 4
F1, F2 @ –7 dBFS
Test
Temp Level
25°C II
25°C II
25°C II
25°C II
25°C II
25°C V
25°C II
25°C II
25°C V
25°C II
25°C II
25°C V
Full V
Full V
AD6644AST-40
Min
Typ
Max
74.5
74.0
73.5
74.5
74.0
73.0
92
90
85
93
92
92
100
90
AD6644AST-65
Min
Typ Max
72
74.5
72
74.0
72
73.5
72
74.5
72
74.0
73.0
83
92
83
90
85
85
93
85
92
92
100
90
Unit
dB
dB
dB
dB
dB
dB
dBc
dBc
dBc
dBc
dBc
dBc
dBFS
dBc
ANALOG INPUT BANDWIDTH
25°C V
250
250
MHz
NOTES
1All ac specifications tested by driving ENCODE and ENCODE differentially.
2AVCC = 5 V to 5.25 V for rated ac performance.
3Analog input signal power swept from –7 dBFS to –100 dBFS.
4F1 = 15 MHz, F2 = 15.5 MHz.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS (AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = Maximum Conversion Rate MSPS; TMIN =
–25؇C, TMAX = +85؇C, CLOAD = 10 pF)
Parameter
Name
Temp
Test
Level
AD6644AST-40/65
Min
Typ
Max
Unit
ENCODE INPUT PARAMETERS1
Encode Period1 @ 65 MSPS
Encode Period1 @ 40 MSPS
Encode Pulsewidth High2 @ 65 MSPS
Encode Pulsewidth Low @ 65 MSPS
tENC
Full
V
tENC
Full
V
tENCH
Full
IV
tENCL
Full
IV
15.4
ns
25
ns
6.2
7.7
9.2
ns
6.2
7.7
9.2
ns
ENCODE/DATA READY
Encode Rising to Data Ready Falling
Encode Rising to Data Ready Rising
@ 65 MSPS (50% Duty Cycle)
@ 40 MSPS (50% Duty Cycle)
tDR
Full
IV
tE_DR
Full
IV
Full
IV
2.6
3.4
4.6
ns
10.3
tENCH + tDR
11.1
12.3
ns
15.1
15.9
17.1
ns
ENCODE/DATA (D13:0), OVR
ENC to DATA Falling Low
tE_FL
Full
IV
ENC to DATA Rising Low
tE_RL
Full
IV
ENCODE to DATA Delay (Hold Time)3
tH_E
Full
IV
ENCODE to DATA Delay (Setup Time)4
tS_E
Encode = 65 MSPS (50% Duty Cycle)
Full
IV
Encode = 40 MSPS (50% Duty Cycle)
Full
IV
3.8
5.5
9.2
ns
3.0
4.3
6.4
ns
3.0
4.3
6.4
ns
tENC – tE_FL
6.2
9.8
11.6
ns
15.9
19.4
21.2
ns
REV. 0
–3–

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