AD28MSP01 Ver la hoja de datos (PDF) - Analog Devices

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Fabricante

AD28MSP01

PSTN Signal Port

Analog Devices 

Since the resample phase is locked to RCONV, it can be ad-

vanced or slipped by writing a signed-magnitude value to the

Receive Phase Adjust Register (Control Register 2). The phase

advance or slip is equal to the master clock period (13.824 MHz)

multiplied by the signed-magnitude 9-bit value in Control

Register 4.

The change in phase requires a maximum of two RCONV

cycles to complete. If the value written to Control Register 4 is

less than the oversampling ratio, then the change will complete

in one RCONV cycle.

Control Registers

The AD28msp01’s six control registers configure the device for

various operating modes including filter bypass and power-

down. The AD28msp01’s host processor can read and write to

AD28msp01

the control register through the AD28msp01’s serial port

(SPORT).

The control registers should be set up for the desired mode of

operation before bringing the AD28msp01 out of power-down

(by writing ones to the PWDA and PWDD bits in Control

Register 1).

The control registers are cleared (set to 0x0000) when the

AD28msp01 is reset.

The sampling rate should be set before writing ones to the

power-down bits. Changing the sampling rate at any other time

will force a soft reset. For more information about soft resets,

refer to the end of this section of the data sheet.

NOTE: Reserved bits should always be cleared to 0.

Control Register 0

address = 0x00

This register is used to:

• Enable/disable the resampling interpolation filter

• Set the external TSYNC clock rate

• Select the sampling rate

• Select the operating mode

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0000 000 00 000000

INTEN

Interpolation filter enable

1 = enabled; 0 = disabled

TS3-0

TSYNC Rate (Hz)

0000 = 9600

0001 = 8000

0010 = 7200

0011 = 4800

0100 = 2400

0101 = 1200

0110 = 600

0111 = 19200

1000 = 14400

1001 = 12000

SR1-0

Sampling Rate (kHz)

00 = 9.6

01 = 8.0

10 = 7.2

11 = Reserved

OP2-0

Operating Modes

000 = Asynchronous fallback mode

001 = Reserved

010 = Reserved

011 = Reserved

100 = V.32 TSYNC

101 = V.32 Internal Sync

110 = V.32 Loopback

111 = Async. fallback mode TSYNC

Control Register 1

address = 0x01

This register is used to:

• Increase the sampling rate to 8/7 the rate selected in Control Register 0

• Power down the device

• Bypass the digital filters

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FB2 FB1 FB0

0 00 0 0 00 0 00 00 00 0 0

SA87

When set to a 1, this bit increases the

sampling rate to 8/7 of the programmed

rate:

(8/7) 9.6 kHz = 10.97 kHz,

(8/7) 8.0 kHz = 9.14 kHz,

(8/7) 7.2 kHz = 8.23 kHz

PWDA

Power Down Analog

1 = Standard Operation

0 = Low Power

PWDD

Power Down Digital

1 = Standard Operation

0 = Low Power

FB2-0

Filter Bypass

Configuration

FB2 FB1 FB0

0 0 0=

0 0 1=

0 1 0=

0 1 1=

1 0 0=

1 0 1=

1 1 0=

1 1 1=

No filter bypass (default)

Reserved

ADC Hi pass filter bypassed

ADC Hi and Lo pass filter bypassed

DAC filter bypassed

Reserved

DAC and ADC Hi pass filters bypassed

DAC, ADC Hi and ADC Lo pass filters bypassed

REV. A

–7–

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