CS51221 Ver la hoja de datos (PDF) - Cherry semiconductor

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Fabricante

CS51221

Enhanced Voltage Mode PWM Controller

Cherry semiconductor 

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Theory of Operation

VOUT

Feed Forward Voltage Mode Control

VCOMP

In conventional voltage mode control, the ramp signal has

fixed rising and falling slope. The feedback signal is

derived solely from the output voltage. Consequently,

voltage mode control has inferior line regulation and audio

susceptibility.

Feed forward voltage mode control derives the ramp sig-

nal from the input line, as shown in Fig.1. Therefore, the

ramp of the slope varies with the input voltage. At the start

of each switch cycle, the capacitor connected to the FF pin

is charged through a resistor connected to the input volt-

age. Meanwhile, the Gate output is turned on to drive an

external power switching device. When the FF pin voltage

reaches the error amplifier output VCOMP, the PWM com-

parator turns off the Gate, which in turn opens the external

switch. Simultaneously, the FF capacitor is quickly dis-

charged to 0.3V.

Overall, the dynamics of the duty cycle are controlled by

both input and output voltages. As illustrated in Fig. 2,

with a fixed input voltage the output voltage is regulated

solely by the error amplifier. For example, an elevated

output voltage reduces VCOMP which in turn causes duty

cycle to decrease. However, if the input voltage varies, the

slope of the ramp signal will react immediately which pro-

vides a much improved line transient response. As an

example shown in Fig.3, when the input voltage goes up,

the rising edge of the ramp signal increases which reduces

duty cycle to counteract the change.

VIN

Power Stage

VOUT

FF

VIN

RTCT

GATE

Figure 2: Pulse Width Modulated by Output Current with Constant

Input Voltage.

VIN

VCOMP

FF

IOUT

RTCT

GATE

Figure 3: Pulse Width modulated by Input Voltage with constant

Output Current.

R

FF

COMP

C

GATE

Latch & Driver

Feedback Network

PWM

-

FB

+

Error Amplifier

+-

Figure 1: Feed Forward Voltage Mode Control.

Powering the IC & UVL

The Under Voltage Lockout (UVL) comparator has two

voltage references; the start and stop thresholds. During

power-up, the UVL comparator disables VREF (which in-

turn disables the entire IC) until the controller reaches its

VCC start threshold. During power-down, the UVL com-

parator allows the controller to operate until the VCC stop

threshold is reached. The CS51221 requires only 50µA dur-

ing startup. The output stage is held at a low impedance

state in lock out mode.

The feed forward feature can also be employed to provide

a volt-second clamp, which limits the maximum product

of input voltage and turn on time. This clamp is used in

circuits, such as Forward and Flyback converter, to prevent

the transformer from saturating. Calculations used in the

design of the volt-second clamp are presented in the

Design Guidelines section.

During power up and fault conditions, the soft-start

clamps the Comp pin voltage and limits the duty cycle.

The power up transition tends to generate temporary duty

cycles much greater than the steady state value due to the

low output voltage. Consequently, excessive current

stresses often take place in the system. Soft Start technique

alleviates this problem by gradually releasing the clamp on

the duty cycle to eliminate the in-rush current. The dura-

tion of the Soft Start can be programmed through a capaci-

tance connected to the SS pin. The constant charging cur-

rent to the SS pin is 50µA (typ).

7

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