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MSM82C51A-2

UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER

Oki Electric Industry 

¡ Semiconductor

MSM82C51A-2RS/GS/JS

Pin Description

D0 to D7 (l/O terminal)

This is bidirectional data bus which receive control words and transmits data from the CPU and

sends status words and received data to CPU.

RESET (Input terminal)

A “High” on this input forces the MSM82C51A-2 into “reset status.”

The device waits for the writing of “mode instruction.”

The min. reset width is six clock inputs during the operating status of CLK.

CLK (Input terminal)

CLK signal is used to generate internal device timing.

CLK signal is independent of RXC or TXC.

However, the frequency of CLK must be greater than 30 times the RXC and TXC at Synchronous

mode and Asynchronous “x1” mode, and must be greater than 5 times at Asynchronous “x16”

and “x64” mode.

WR (Input terminal)

This is the “active low” input terminal which receives a signal for writing transmit data and

control words from the CPU into the MSM82C51A-2.

RD (Input terminal)

This is the “active low” input terminal which receives a signal for reading receive data and

status words from the MSM82C51A-2.

C/D (Input terminal)

This is an input terminal which receives a signal for selecting data or command words and status

words when the MSM82C51A-2 is accessed by the CPU.

If C/D = low, data will be accessed.

If C/D = high, command word or status word will be accessed.

CS (Input terminal)

This is the “active low” input terminal which selects the MSM82C51A-2 at low level when the

CPU accesses.

Note: The device won’t be in “standby status”; only setting CS = High.

Refer to “Explanation of Standby Status.”

TXD (output terminal)

This is an output terminal for transmitting data from which serial-converted data is sent out.

The device is in “mark status” (high level) after resetting or during a status when transmit is

disabled. It is also possible to set the device in “break status” (low level) by a command.

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