74LVT573PW Ver la hoja de datos (PDF) - NXP Semiconductors.

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74LVT573PW

3.3 V octal D-type transparent latch; 3-state

NXP Semiconductors. 

Nexperia

74LVT573

3.3 V octal D-type transparent latch; 3-state

tW

VI 90 %

negative

pulse

VM

10 %

0V

tf

VI

positive

pulse

tr

90 %

VM

10 %

0V

tW

VM

tr

tf

VM

VCC

VI

PULSE

GENERATOR

VO

DUT

RT

VEXT

RL

CL

RL

001aae235

Test data is given in Table 9.

Definitions test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

VEXT = Test voltage for switching times.

Fig 11. Test circuitry for switching times

Table 9.

Input

VI

2.7 V

Test data

fi

 10 MHz

tW

500 ns

tr, tf

 2.5 ns

Load

CL

50 pF

RL

500 

VEXT

tPHZ, tPZH

GND

tPLZ, tPZL

6V

tPLH, tPHL

open

74LVT573

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 8 — 22 November 2011

© Nexperia B.V. 2017. All rights reserved

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