74LVT573PW Ver la hoja de datos (PDF) - NXP Semiconductors.
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74LVT573PW Datasheet PDF : 17 Pages
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Nexperia
74LVT573
3.3 V octal D-type transparent latch; 3-state
5.2 Pin description
Table 2. Pin description
Symbol
Pin
OE
1
D0 to D7
2, 3, 4, 5, 6, 7, 8, 9
GND
10
LE
11
Q0 to Q7
19, 18, 17, 16, 15, 14, 13, 12
VCC
20
6. Functional description
Description
output enable input (active LOW)
data input
ground (0 V)
latch enable (active HIGH)
data output
supply voltage
6.1 Function table
Table 3. Function table [1]
Operating mode
Control OE
Load and read register
L
enable
Latch and read register
L
Hold
L
Disable outputs
H
Control LE
H
L
L
H
Input Dn
L
H
l
h
X
X
Dn
[1] H = HIGH voltage level;
L = LOW voltage level;
= HIGH-to-LOW latch enable transition;
h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition;
l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition;
Z = high-impedance OFF-state;
NC = no change;
X = don’t care.
7. Limiting values
Internal register Output Qn
L
L
H
H
L
L
H
H
NC
NC
NC
Z
Dn
Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
VI
input voltage
VO
output voltage
IIK
input clamping current
IOK
output clamping current
output in OFF-state or HIGH-state
VI < 0 V
VO < 0 V
0.5
+4.6
V
[1] 0.5
+7.0
V
[1] 0.5
+7.0
V
-
50
mA
-
50
mA
IO
output current
output in LOW-state
output in HIGH-state
-
128
mA
-
64
mA
74LVT573
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 22 November 2011
© Nexperia B.V. 2017. All rights reserved
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