74LVCH1T45GF Ver la hoja de datos (PDF) - NXP Semiconductors.
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74LVCH1T45GF Datasheet PDF : 30 Pages
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NXP Semiconductors
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
Table 11. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C [1][2]
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
1.8 V
VCC(A) and VCC(B)
2.5 V
3.3 V
CPD
power dissipation A port: (direction A to B);
2
3
3
capacitance
B port: (direction B to A)
A port: (direction B to A);
15
16
16
B port: (direction A to B)
[1] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
[2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω.
Unit
5.5 V
4
pF
18
pF
Table 12. Dynamic characteristics for temperature range −40 °C to +85 °C
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7
Symbol Parameter
Conditions
VCC(B)
Unit
1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V
Min Max Min Max Min Max Min Max Min Max
VCC(A) = 1.4 V to 1.6 V
tPLH
LOW to HIGH
propagation delay
A to B
B to A
2.8 21.3 2.4 17.6 2.0 13.5 1.7 11.8 1.6 10.5 ns
2.8 21.3 2.6 19.1 2.3 14.9 2.3 12.4 2.2 12.0 ns
tPHL
HIGH to LOW
A to B
propagation delay B to A
2.6 19.3 2.2 15.3 1.8 11.8 1.7 10.9 1.7 10.8 ns
2.6 19.3 2.4 17.3 2.3 13.2 2.2 11.3 2.3 11.0 ns
tPHZ
HIGH to OFF-state DIR to A
propagation delay DIR to B
3.0 18.7 3.0 18.7 3.0 18.7 3.0 18.7 3.0 18.7 ns
3.5 24.8 3.5 23.6 3.0 11.0 3.3 11.3 2.8 10.3 ns
tPLZ
LOW to OFF-state DIR to A
propagation delay DIR to B
2.4 11.4 2.4 11.4 2.4 11.4 2.4 11.4 2.4 11.4 ns
2.8 18.3 3.0 17.2 2.5 9.4 3.0 10.1 2.5 9.4 ns
tPZH
OFF-state to HIGH DIR to A [1] - 39.6 - 36.3 - 24.3 - 22.5 - 21.4 ns
propagation delay DIR to B [1] - 32.7
-
29.0
- 24.9 - 23.2 - 21.9 ns
tPZL
OFF-state to LOW DIR to A [1] - 44.1 - 40.9 - 24.2 - 22.6 - 21.3 ns
propagation delay DIR to B [1] - 38.0
-
34.0
- 30.5 - 29.6 - 29.5 ns
VCC(A) = 1.65 V to 1.95 V
tPLH
LOW to HIGH
propagation delay
A to B
B to A
2.6 19.1 2.2 17.7 2.2 9.3 1.7 7.2 1.4 6.8 ns
2.4 17.6 2.2 17.7 2.3 16.0 2.1 15.5 1.9 15.1 ns
tPHL
HIGH to LOW
A to B
propagation delay B to A
2.4 17.3 2.0 14.3 1.6 8.5 1.8 7.1 1.7 7.0 ns
2.2 15.3 2.0 14.3 2.1 12.9 2.0 12.6 1.8 12.2 ns
tPHZ
HIGH to OFF-state DIR to A
propagation delay DIR to B
2.9 17.1 2.9 17.1 2.9 17.1 2.9 17.1 2.9 17.1 ns
3.2 24.1 3.2 21.9 2.7 11.5 3.0 10.3 2.5 8.2 ns
tPLZ
LOW to OFF-state DIR to A
propagation delay DIR to B
2.4 10.5 2.4 10.5 2.4 10.5 2.4 10.5 2.4 10.5 ns
2.5 17.6 2.6 16.0 2.2 9.2 2.7 8.4 2.4 6.4 ns
74LVC_LVCH1T45_2
Product data sheet
Rev. 02 — 19 January 2010
© NXP B.V. 2010. All rights reserved.
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