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73K222AU

Single-Chip Modem Modem with UART

TDK Corporation 

73K222AU

Single-Chip Modem

with UART

PIN DESCRIPTION (continued)

MICROPROCESSOR INTERFACE (STNDLN = 0)

(See Figure 2: Dual-port mode)

NAME

DIP PLCC TYPE DESCRIPTION

MA0-MA2

12-14 14-16

I

Modem Address Control. These lines carry register addresses

for the modem registers and should be valid throughout any read

or write operation.

DATA

22

24

I/O Serial Control Data. Serial control data to be read/written is

clocked in/out on the falling edge of the DCLK pin. The direction

of data transfer is controlled by the state of the RD pin. If the RD

pin is active (low) the DATA line is an output. Conversely, if the

RD pin is inactive (high) the DATA line is an input.

RD

23

25

I

Read. A low on this input informs the 73K222AU that control

data or status information is being read by the processor from a

modem register.

WR

26

28

I

Write. A low on this input informs the 73K222AU that control

data or status information is available for writing into a modem

register. The procedure for writing is to shift in data LSB first on

the DATA pin for eight consecutive cycles of DCLK and then to

pulse WR low. Data is written on the rising edge of WR.

DCLK

11

13

I

Data Clock. The falling edge of this clock is used to strobe

control data for the modem registers in or out on the DATA pin.

The normal procedure for a write is to shift in data LSB first on

the DATA pin for eight consecutive cycles of DCLK and then to

pulse WR low. Data is written on the rising edge of WR. The

falling edge of the RD signal must continue for eight cycles of

DCLK in order to read all eight bits of the reference register.

Read data is provided LSB first. Data will not be output unless

the RD signal is active.

INT

2

3

O

(with weak pull-up) Modem Interrupt. This output signal is used

to inform the modem processor that a change in a modem detect

flag has occurred. The processor must then read the Modem

Detect Register to determine which detect triggered the interrupt.

INT will stay active until the processor reads the Modem Detect

Register or does a full reset.

MPRST*

8

10

O

Microprocessor Reset. This output signal is used to provide a

hardware reset to the microprocessor. This signal is high if the

RESET pin is high or the MCR bit D3 (OUT1) bit is set.

* NOTE: The µPRST pin is an upgraded function which was not included in the initial definition of the

73K222AU.

8

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