MAX532 Ver la hoja de datos (PDF) - Maxim Integrated
Número de pieza
componentes Descripción
Fabricante
MAX532 Datasheet PDF : 16 Pages
| |||
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
Table 1. tRC Delay Times
VPULL-UP (V)
4.5
4.5
4.5
4.5
4.5
11.4
11.4
11.4
11.4
11.4
13.5
13.5
13.5
13.5
13.5
C (pF)
20
35
50
100
150
20
35
50
100
150
20
35
50
100
150
RP (kΩ)
1
1
1
1
1
3
3
3
3
3
3
3
3
3
3
tRC (ns)
15
27
38
76
114
14
25
35
71
106
12
21
29
59
88
With the values of tRC given in Table 1, tCSS0 is always
given by tDV + tDS. For different values of R or C, tRC
must be calculated to determine tCSS0.
Additionally, the maximum clock frequency is limited to
1
fCLK (max) = ————————————— .
2 x (tDO + tRC -15ns + tDS)
For example, with tRC = 15ns (5V ±10% supply with
1kΩ pull-up), the maximum clock frequency is 2MHz.
VREF_
R
R
Digital-to-Analog Section
Figure 8 shows a simplified circuit diagram for one of
the DACs and the output amplifier.
A segmented scheme is used to improve linearity,
whereby the two MSBs of the 12-bit data word are
decoded to drive the three switches, SA, SB, and SC.
The remaining ten bits drive the switches S0 through S9
in a standard R-2R ladder configuration.
Each of the switches, SA, SB, and SC, steers 1/4 of the
total reference current with the remaining 1/4 passing
through the R-2R section.
The output amplifier and feedback resistor perform the
current-to-voltage conversion, giving the following:
VOUT_ = -D x VREF_,
where _ denotes A or B, and D is the fractional representa-
tion of the digital word. (D can be set from 0 to 4095/4096.)
+12V to +15V
VDD
RFBA
VIN VREFA
DACA
DGND
VSS
VOUTA
VOUT
MAX532
AGNDA
-12V to -15V
Figure 9. Unipolar Binary Operation
R
2R
2R
2R
2R
SC
SB
SA
S9
2R
2R
S8
S0
SHOWN FOR ALL 1s ON DAC
2R
R/2
RFB_
VOUT_
AGND_
Figure 8. Simplified D/A Circuit Diagram
______________________________________________________________________________________ 11
Share Link: 