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X40010

Dual Voltage Monitor with Integrated CPU Supervisor

Xicor -> Intersil 

X40010/X40011/X40014/X40015 – Preliminary

Setting a Lower VTRIPx Voltage (x=1, 2)

In order to set VTRIPx to a lower voltage than the

present value, then VTRIPx must first be “reset” accord-

ing to the procedure described below. Once VTRIPx

has been “reset”, then VTRIPx can be set to the desired

voltage using the procedure described in “Setting a

Higher VTRIPx Voltage”.

Resetting the VTRIPx Voltage

To reset a VTRIPx voltage, apply the programming volt-

age (Vp) to the WDO pin before a START condition is

set up on SDA. Next, issue on the SDA pin the Slave

Address A0h followed by the Byte Address 03h for

VTRIP1 and 0Bh for VTRIP2, followed by 00h for the

Data Byte in order to reset VTRIPx. The STOP bit fol-

lowing a valid write operation initiates the programming

sequence. Pin WDO must then be brought LOW to

complete the operation.

After being reset, the value of VTRIPx becomes a nomi-

nal value of 1.7V or lesser.

Note: This operation does not corrupt the memory

array.

CONTROL REGISTER

The Control Register provides the user a mechanism

for changing the Block Lock and Watchdog Timer set-

tings. The Block Lock and Watchdog Timer bits are

nonvolatile and do not change when power is removed.

The Control Register is accessed with a special pre-

amble in the slave byte (1011) and is located at

address 1FFh. It can only be modified by performing a

byte write operation directly to the address of the regis-

ter and only one data byte is allowed for each register

write operation. Prior to writing to the Control Register,

the WEL and RWEL bits must be set using a two step

process, with the whole sequence requiring 3 steps.

See "Writing to the Control Registers" on page 7.

The user must issue a stop, after sending this byte to

the register, to initiate the nonvolatile cycle that stores

WD1, WD0, PUP1, PUP0, BP1, and BP0. The X40010/

11/14/15 will not acknowledge any data bytes written

after the first byte is entered.

The state of the Control Register can be read at any

time by performing a random read at address 01Fh,

using the special preamble. Only one byte is read by

each register read operation. The master should sup-

ply a stop condition to be consistent with the bus proto-

col, but a stop is not required to end this operation.

7

6

5

4

PUP1 WD1 WD0 BP

3

2

1

0

0 RWEL WEL PUP0

RWEL: Register Write Enable Latch (Volatile)

The RWEL bit must be set to “1” prior to a write to the

Control Register.

Figure 4. Sample VTRIP Reset Circuit

VTRIP1

Adj.

V2FAIL

RESET

VTRIP2

Adj.

4.7K

1

8

3 SOIC 7

2 X4001x 6

4

5

VP

Adjust

Run

µC

SCL

SDA

REV 1.3.4 7/12/02

www.xicor.com

Characteristics subject to change without notice. 5 of 25

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