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SC28L202A1D

Dual universal asynchronous receiver/transmitter (DUART)

Philips Electronics 

Philips Semiconductors

Dual UART

Objective specification

SC28L202

CONFIGURATION FOR 68XXX BUS INTERFACE (MOTOROLA)

Symbol

Pin

type

Name and Function

I/M

I

Bus Configuration: When low configures the bus interface to the Conditions shown in this table.

D0–D7

I/O

Data Bus: Bi–directional 3–State data bus used to transfer commands, data and status between the DUART and the

CPU. D0 is the least significant bit.

CSN

I

Chip Enable: Active–Low input signal. When Low, data transfers between the CPU and the DUART are enabled on

D0–D7 as controlled by the R/WN and A0–A6 inputs. When High, places the D0–D7 lines in the 3–State condition.

R/WN

I

Read/Write: Input Signal. When CSN is low R/WN high input a read cycle, when low a write cycle.

IACKN

I

Interrupt Acknowledge: Active low input indicates an interrupt acknowledge cycle. Usually asserted by the CPU in

response to an interrupt request. When asserted places the interrupt vector on the bus and asserts DACKN.

DACKN O

Data Transfer Acknowledge: A 3–State active –low output asserted in a write, read, or interrupt acknowledge cycle to

indicate proper transfer of data between the CPU and the DUART.

A6–A0

I

Address Inputs: Select the DUART internal registers and ports for read/write operations.

RESETN I

Reset: A low level clears internal registers (SR A , SR B, IMR, ISR, OPR, OPCR), places I/O[7:0] A and B at high

impedance input state, stops the counter/timer, and puts Channels A and B in the inactive state, with the TxD A and

TxD B outputs in the mark (High) state. Sets MR pointer to MR1, 9600 baud, 1 start, no parity and 1 stop bit(s). (See

Reset Table)

IRQN

O

Interrupt Request: Active–Low, open–drain, output which signals the CPU that one or more of the eighteen (18)

maskable interrupting conditions are true.

X1 / Sclk I

Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When

a crystal is used, a capacitor must be connected from this pin to ground (see Figure 9).

X2

O

Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this

pin to ground (see Figure 9). If Sclk is driven from an external source, this pin must be left open.

RxD A

I

Channel A Receiver Serial Data Input: The least significant bit is received first. “Mark” is High; “space” is Low.

RxD B

I

Channel B Receiver Serial Data Input: The least significant bit is received first. “Mark” is High; “space” is Low.

TxD A

O

Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the

“mark” condition when the transmitter is disabled, idle or when operating in local loop back mode. “Mark” is High;

“space” is Low.

TxD B

O

Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the ‘mark’

condition when the transmitter is disabled, idle, or when operating in local loop back mode. ‘Mark’ is High; ‘space’ is

Low.

I/O[7:0]A I/O

General–purpose input and output ports channel A: The character of these pins is controlled by I/OPCR. They may

be inputs or outputs and will present many internal clocks and interrupt signals: RTS, CTS, DTR, DSR etc. All have

change of state detectors and the input is always active. These pins are set to input only when addressed from the

low order 16 address space. When these pins are configured for interrupt type signals (RxRDY, TxRDY, C/TRDY)

They switch to open drain outputs.

I/O[7:0}B I/O

General–purpose input and output ports channel B: The character of these pins is controlled by I/OPCR. They may

be inputs or outputs and will present many internal clocks and interrupt signals: RTS, CTS, DTR, DSR etc. All have

change of state detectors and the input is always active. These pins are set to output only when addressed from the

low order 16 address space. When these pins are configured for interrupt type signals (RxRDY, TxRDY, C/TRDY)

They switch to open drain outputs

Vcc

Power Power Supply: +3.3 or +5V supply input ± 10% (4 Vcc Pins) ). Operation is assured from 2.97 to 5.5 volts. Timing

parameters are specified with respect to the Vcc being at 3.3 of 5.0 volts +/– 10%

Vss

Power Ground (5 Vss Pins)

2000 Feb 10

4

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