MG64PB28 Ver la hoja de datos (PDF) - Oki Electric Industry

Número de pieza

componentes Descripción

Fabricante

MG64PB28

0.25µm Embedded DRAM/Customer Structured Arrays

Oki Electric Industry 

––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– s MG63P/64P/65P s

I/O base cells

Configurable I/O pads

for VDD, VSS, or I/O

Separate power bus (VDDC, VSSC) for

internal core logic (2nd metal/3rd metal)

1, 2, 3, 4, or 5 layer

metal

interconnection in

core area

Core base cell

with 4 transistors

VDD, VSS pads (4) in each

corner for wafer probing only

Separate power bus (VDDO, VSSO) over I/O cell

for output buffers (2nd metal/3rd metal)

Figure 7. MG65P Array Architecture

MG63P/64P/65P CSA Layout Methodology

The procedure to design, place, and route a CSA follows.

1. Select suitable base array frame from the available predefined sizes. To select an array size:

- Identify megacell functions (e.g. embedded SDRAM) required and minimum array size to

hold macrocell functions.

- Add together all the area occupied by the required random logic and macrocells and select

the optimum array.

2. Make a floor plan for the design’s megacells.

- Oki Design Center engineers verify the master slice and review simulation.

- Oki Design Center or customer engineers floorplan the array using Oki’s supported Cadence

DP3 or Gambit GFP and customer performance specifications.

- Using Oki CAD software, Design Center engineers remove the SOG transistors and replace

them with diffused memory macrocells to the customer’s specifications.

Oki Semiconductor

3

Share Link: