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Fabricante

VSC7130RC

Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC7130

Dual Repeater/Retimer

for Fibre Channel and Gigabit Ethernet

Clock and Data Recovery (CDR)

Two Clock and Data Recovery Units (CDR) are included in the VSC7130 in order to improve signal quality of

serial data by amplification and jitter attenuation. Figure 7 shows a block diagram of each CDR with its corre-

sponding Signal Detect Unit (SDU). Table 2 shows how each CDR may be configured as either a repeater or a

retimer using the MODE0, MODE1 and T/R pins or via the Two-Wire Interface by programming the MODEDIS,

T/RDIS and ITRx register bits.

Figure 7: CDRx/SDUx Block Diagram

BYPx

Serial In

SELRTx

(derived from

MODE[1:0], T/R,

MODEDIS, T/RDIS and

and ITRx)

D

Q

REPEATERx

CLKO

OSGENx

OSGxSEL

Baud Rate Clock

(from CMU)

OSGENxA 0

OSGENxB 1

Analog Signal Detect In

(from input buffer)

ASDDISx

RLLDISx

K28DISx

KWINDx(5:0)

1 Serial Out

0

1

0

D

Q

RETIMERx

UNDERx

OVERx

ADDx

DROPx

D

SDUx

SDx

PSDx

ASDx

RLLx

K28x

D

HUB

Support

OSREC0A

OSREC0B

IDLEx

ARBx

OPENx

CLSx

LIPF7,F7x

LIPF8,F7X

LIPF7,Xx

LIPF8,Xx

LIPYXx

LIPFFx

NLIPF8x

OSRxA

OSRxB

G52297-0, Rev 4.0

04/02/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

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