VSC7130RC(2000) Ver la hoja de datos (PDF) - Vitesse Semiconductor

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VSC7130RC
(Rev.:2000)

Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Dual Repeater/Retimer

for Fibre Channel and Gigabit Ethernet

Advance Product Information

VSC7130

incoming data is not necessarily at the same frequency as the internal baudrate clock, so special Fibre Channel

Ordered Sets, called Fill Words, are added or dropped from the data stream in order to accommodate this speed

difference. The rules for adding and dropping Fill Words are delineated in documents generated by the T11

committee: FC-PH, FC-PH2, FC-PH3, FC-AL, FC-AL2 and FC-AL3 (in progress). The VSC7130 is fully

compliant with these rules.

A detailed block diagram of the Retimer is shown below. Incoming data goes into a Clock Recovery Unit

(CRU) where the data is recovered and resampled. Recovered data and recovered clock are sent to the Add/

Drop FIFO where the data is stored using the recovered clock. Data is removed from the Add/Drop FIFO and

resynchronized by the Retransmitting Flip-Flop using the internally generated baud rate clock derived from

REFI. The output of the Flip-Flop is recovered serial data which is synchronous to the low-jitter baud rate

clock and complies with all jitter specifications for Fibre Channel.

Figure 5: Retimer Block Diagram

INPUT

DATA

Clock

Recovery

Unit

D

Q

CLKI CLKO

D

Q

CLKI

CLK

ADD/DROP

FIFO

To RTMRxC Register

UNDERx

OVERx

ADDx

DROPx

Retransmit

Flip-Flop

D

Q

CLK

OUTPUT

DATA

1.0625 GHz Internal Baud Rate Clock

The internally generated baud rate clock (nominally 1.0625 GHz) is used by the Retimer for several func-

tions. First, it provides the timing reference for the Clock Recovery Unit. Second, it clocks data out of the

FIFO. Third, it retimes the retransmitted output data. The quality of the baud rate clock will impact the jitter

tolerance of the Clock Recovery Unit and the jitter generation of the Retransmitter Flip-Flop. The signal quality

of the internally generated baud rate clock is directly related to jitter on REFI and power supply noise. The user

is encouraged to minimize both REFI jitter and power supply noise in order to maximize jitter tolerance at the

input and minimize jitter generation at the output.

In the Add/Drop FIFO, a phase detector monitors the phase difference between the recovered clock and the

internally generated baud rate clock to determine when to add or drop Fill Words. Fill Words can only be

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© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52297-0, Rev. 2.3

1/17/00

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