Hardware Design Considerations
Board IVDD
10 Ω
10 µF
0.1 µF
PLL VDD Pin
GND
Figure 1. System PLL VDD Power Filter
3.2 USB Power Filtering
To minimize noise, external filters are required for each of the USB power pins. The filter shown in Figure 2 should be
connected between the board EVDD and each of the USBVDD pins. The resistor and capacitors should be placed as close to the
dedicated USBVDD pin as possible.
Board EVDD
0Ω
10 µF
0.1 µF
USB VDD Pin
GND
Figure 2. USB VDD Power Filter
NOTE
In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel
with those shown.
3.3 Supply Voltage Sequencing
Figure 3 shows situations in sequencing the I/O VDD (EVDD), SDRAM VDD (SDVDD), PLL VDD (PVDD), and internal logic /
core VDD (IVDD). The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences.
Both SDVDD (2.5V or 1.8V) and EVDD are specified relative to IVDD.
MCF5301x Data Sheet, Rev. 5
6
Preliminary—Subject to Change Without Notice
Freescale Semiconductor