CY3688 Ver la hoja de datos (PDF) - Cypress Semiconductor
Número de pieza
componentes Descripción
Fabricante
CY3688 Datasheet PDF : 11 Pages
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Introduction
Figure 1-1. Block Diagram
D6
VBATT
D8
VDD
D3
VIO
OSC1
CLK
J5
U5
J4
Inverter
RESET_N
CS_N
U2
USB
Connector
VBUS
J11
J10
EXT
PWR
U3
PWR
REG
U1
TX2UL
ULPI BUS
J1
T&MT
Connector
R12
R7
R13
VIO
VDD
1.2.2
1.2.3
1.2.4
Power Supply
The TX2UL device VDD and VIO power supplies are expected to be supplied from the ULPI
connector. VBATT power supply can be supplied from VBUS or the external power supply included
with the kit. To power the board using VBUS, connect pin 2 and 3 of J11. Make sure the USB cable is
connected to a host USB port. The other option is to use the included power supply and connect 1
and 2 of J11 (default configuration).
The system is equipped with a method to check the power consumption of the TX2UL device.
Measure the voltage drop across R7, R13, and R12, this is the current consumed by VDD, VIO, and
VBATT consecutively.
ULPI Interface
UTMI+ Low Pin Interface (ULPI) is a standard interface developed to interface a link to a USB 2.0
PHY. It supports an 8-bit wide SDR data path. The primary I/Os of this block support multirange
LVCMOS signaling from 1.8 V to 3.3 V. The level used is automatically selected by the voltage
applied to VIO and can be set at any voltage between 1.8 V and 3.3 V.
The ULPI interface is mapped to J1 for interconnection to development platforms. The connector
pinout is as specified by the ULPI specification, page 92. Use the schematic attached in the CD/DVD
ROM as a reference.
CS_N and RESET
The TX2UL device uses CS_N and RESET_N as active low inputs. In case this system is used with
a link with active high GPIO operation, an option is available to invert these signals. The default is J4
and J5; connect 1 and 2 for direct connection from link. Connecting 2 and 3 will invert these signals.
6
CY3688 MoBL-USB™ TX2UL Development Kit Guide, Doc. # 001-46448 Rev. *C
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