DM74LS112ACW Ver la hoja de datos (PDF) - Fairchild Semiconductor

Número de pieza

componentes Descripción

Fabricante

DM74LS112ACW

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

Fairchild Semiconductor 

Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Symbol

Parameter

Conditions

Typ

Min

Max

(Note 6)

Units

VI

Input Clamp Voltage

VOH

HIGH Level

Output Voltage

VOL

LOW Level

Output Voltage

II

Input Current @ Max

Input Voltage

VCC = Min, II = −18 mA

VCC = Min, IOH = Max

VIL = Max, VIH = Min

VCC = Min, IOL = Max

VIL = Max, VIH = Min

IOL = 4 mA, VCC = Min

VCC = Max, VI = 7V

J, K

Clear

Preset

−1.5

V

2.7

3.4

V

0.35

0.5

V

0.25

0.4

0.1

0.3

mA

0.3

Clock

0.4

IIH

HIGH Level Input Current

VCC = Max, VI = 2.7V

J, K

Clear

Preset

20

60

µA

60

Clock

80

IIL

LOW Level Input Current

VCC = Max, VI = 0.4V

J, K

Clear

Preset

−0.4

−0.8

mA

−0.8

Clock

−0.8

IOS

Short Circuit Output Current

ICC

Supply Current

Note 6: All typicals are at VCC = 5V, TA = 25°C.

VCC = Max (Note 7)

VCC = Max (Note 8)

−20

−100

mA

4

6

mA

Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs,

where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where VO = 2.125V with the minimum

and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment.

Note 8: With all outputs OPEN, ICC is measured with the Q and Q outputs HIGH in turn. At the time of measurement the clock is grounded.

Switching Characteristics

at VCC = 5V and TA = 25°C

Symbol

Parameter

fMAX

tPLH

tPHL

tPLH

tPHL

tPLH

tPHL

Maximum Clock Frequency

Propagation Delay Time

LOW-to-HIGH Level Output

Propagation Delay Time

HIGH-to-LOW Level Output

Propagation Delay Time

LOW-to-HIGH Level Output

Propagation Delay Time

HIGH-to-LOW Level Output

Propagation Delay Time

LOW-to-HIGH Level Output

Propagation Delay Time

HIGH-to-LOW Level Output

From (Input)

To (Output)

Preset to Q

Preset to Q

Clear to Q

Clear to Q

Clock to Q or Q

Clock to Q or Q

RL = 2 kΩ

CL = 15 pF

CL = 50 pF

Min

Max

Min

Max

30

25

20

24

20

28

20

24

20

28

20

24

20

28

Units

MHz

ns

ns

ns

ns

ns

ns

3

www.fairchildsemi.com

Share Link: