MC74HC109D Ver la hoja de datos (PDF) - Motorola => Freescale

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MC74HC109D

Dual J-K Flip-Flop with Set and Reset

Motorola => Freescale 

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Dual J-K Flip-Flop with

Set and Reset

High–Performance Silicon–Gate CMOS

The MC74HC109 is identical in pinout to the LS109. The device inputs are

compatible with standard CMOS outputs; with pullup resistors, they are

compatible with LSTTL outputs.

This device consists of two J–K flip–flops with individual set, reset, and

clock inputs. Changes at the inputs are reflected at the outputs with the next

low–to–high transition of the clock. Both Q and Q outputs are available from

each flip–flop.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 148 FETs or 37 Equivalent Gates

LOGIC DIAGRAM

5

SET 1

K1 3

CLOCK 1 4

J1 2

RESET 1 1

6 Q1

7 Q1

SET 2 11

K2 13

CLOCK 2 12

J2 14

10 Q2

9 Q2

RESET 2 15

PIN 16 = VCC

PIN 8 = GND

MC74HC109

16

1

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

16

1

D SUFFIX

SOIC PACKAGE

CASE 751B–05

ORDERING INFORMATION

MC74HCXXXN

MC74HCXXXD

Plastic

SOIC

PIN ASSIGNMENT

RESET 1 1

J1 2

16 VCC

15 RESET 2

K1 3

CLOCK 1 4

14 J2

13 K2

SET 1 5

Q1 6

Q1 7

12 CLOCK 2

11 SET 2

10 Q2

GND 8

9 Q2

FUNCTION TABLE

Inputs

Set Reset Clock J

L

H

XX

H

L

XX

L

L

XX

H

H

L

H

H

H

H

H

L

H

H

H

H

H

LX

Outputs

K QQ

X

HL

X

LH

X H* H*

L

LH

L

Toggle

H No Change

H HL

X No Change

* Both outputs will remain high as long as Set and

Reset are low, but the output states are unpre-

dictable if Set and Reset go high simultaneously.

10/95

© Motorola, Inc. 1995

1

REV 6

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