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BC848CPDW1T1

Dual General Purpose Transistors NPN/PNP Duals (Complimentary)

ON Semiconductor 

BC846BPDW1T1, BC847BPDW1T1 Series, BC848CPDW1T1 Series

1.0

D = 0.5

0.2

0.1

0.1

0.05

0.02

0.01 0.01

SINGLE PULSE

0.001

0

1.0

P(pk)

t1

t2

DUTY CYCLE, D = t1/t2

ZqJA(t) = r(t) RqJA

RqJA = 328°C/W MAX

D CURVES APPLY FOR POWER

PULSE TRAIN SHOWN

READ TIME AT t1

TJ(pk) − TC = P(pk) RqJC(t)

10

100

1.0 k

10 k

t, TIME (ms)

Figure 25. Thermal Response

100 k

1.0 M

−200

1s

3 ms

−100

−50

TA = 25°C TJ = 25°C

BC558

−10

BC557

BC556

−5.0

−2.0

−1.0

BONDING WIRE LIMIT

THERMAL LIMIT

SECOND BREAKDOWN LIMIT

−5.0 −10

−30 −45 −65 −100

VCE, COLLECTOR−EMITTER VOLTAGE (V)

Figure 26. Active Region Safe Operating Area

The safe operating area curves indicate IC−VCE lim-

its of the transistor that must be observed for reliable op-

eration. Collector load lines for specific circuits must fall

below the limits indicated by the applicable curve.

The data of Figure 26 is based upon TJ(pk) = 150°C; TC

or TA is variable depending upon conditions. Pulse

curves are valid for duty cycles to 10% provided TJ(pk)

≤ 150°C. TJ(pk) may be calculated from the data in Figure

25. At high case or ambient temperatures, thermal limita-

tions will reduce the power that can be handled to values

less than the limitations imposed by the secondary break-

down.

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