SST25PF080B Ver la hoja de datos (PDF) - Microchip Technology
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SST25PF080B Datasheet PDF : 32 Pages
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SST25PF080B
4.5 Instructions
Instructions are used to read, write (Erase and Pro-
gram), and configure the SST25PF080B. The instruc-
tion bus cycles are 8 bits each for commands (Op
Code), data, and addresses. Prior to executing any
Byte-Program, Auto Address Increment (AAI) program-
ming, Sector-Erase, Block-Erase, Write-Status-Regis-
ter, or Chip-Erase instructions, the Write-Enable
(WREN) instruction must be executed first. The com-
plete list of instructions is provided in Table 4-4. All
instructions are synchronized off a high to low transition
of CE#. Inputs will be accepted on the rising edge of
SCK starting with the most significant bit. CE# must be
driven low before an instruction is entered and must be
driven high after the last bit of the instruction has been
shifted in (except for Read, Read-ID, and Read-Status-
Register instructions). Any low to high transition on
CE#, before receiving the last bit of an instruction bus
cycle, will terminate the instruction in progress and
return the device to standby mode. Instruction com-
mands (Op Code), addresses, and data are all input
from the most significant bit (MSB) first.
TABLE 4-4: DEVICE OPERATION INSTRUCTIONS
Instruction
Read
High-Speed Read
4 KByte Sector-Erase3
32 KByte Block-Erase4
64 KByte Block-Erase5
Chip-Erase
Byte-Program
AAI-Word-Program6
RDSR7
EWSR
WRSR
WREN
WRDI
RDID8
JEDEC-ID
EBSY
DBSY
Read SID
Program SID9
Lockout SID9
Description
Op Code Cycle1
Read Memory
0000 0011b (03H)
Read Memory at higher speed 0000 1011b (0BH)
Erase 4 KByte of
memory array
0010 0000b (20H)
Erase 32 KByte block
of memory array
0101 0010b (52H)
Erase 64 KByte block
of memory array
1101 1000b (D8H)
Erase Full Memory Array
0110 0000b (60H) or
1100 0111b (C7H)
To Program One Data Byte
0000 0010b (02H)
Auto Address Increment
Programming
1010 1101b (ADH)
Read-Status-Register
0000 0101b (05H)
Enable-Write-Status-Register 0101b 0000b (50H)
Write-Status-Register
0000 0001b (01H)
Write-Enable
0000 0110b (06H)
Write-Disable
0000 0100b (04H)
Read-ID
1001 0000b (90H) or
1010 1011b (ABH)
JEDEC ID Read
1001 1111b (9FH)
Enable SO to output RY/BY#
0111 0000b (70H)
status during AAI programming
Disable SO to output RY/BY# 1000 0000b (80H)
status during AAI programming
Read Security ID
1000 1000b (88H)
Program User Security ID area 1010 0101b (A5H)
Lockout Security ID Programming 1000 0101b (85H)
Address
Cycle(s)2
3
3
3
3
3
0
3
3
0
0
0
0
0
3
0
0
0
1
1
0
Dummy
Cycle(s)
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Data
Cycle(s)
1 to ∞
1 to ∞
0
0
0
0
1
2 to ∞
1 to ∞
0
1
0
0
1 to ∞
3 to ∞
0
0
1 to 32
1
0
1. One bus cycle is eight clock periods.
2. Address bits above the most significant bit of each density can be VIL or VIH.
3. 4KByte Sector Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH.
4. 32KByte Block Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH.
5. 64KByte Block Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either at VIL or VIH.
6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data
to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be pro-
grammed into the initial address [A23-A1] with A0=1.
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
2012 Microchip Technology Inc.
DS25134A-page 7
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