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AD10265AZ

Dual Channel, 12-Bit, 65 MSPS A/D Converter with Analog Input Signal Conditioning

Analog Devices 

AD10265

If a low jitter ECL clock is available, another option is to ac-couple

a differential ECL signal to the encode input pins as shown

below. The capacitors shown here should be chip capacitors,

but do not need to be of the low inductance variety.

ECL

GATE

510⍀

0.1␮F

0.1␮F

510⍀

ENCODE

AD10265

ENCODE

GROUNDING AND DECOUPLING

Analog and Digital Grounding

Proper grounding is essential in any high speed, high resolution

system. Multilayer printed circuit boards (PCBs) are recom-

mended to provide optimal grounding and power schemes. The

use of ground and power planes offers distinct advantages:

1. The minimization of the loop area encompassed by a signal

and its return path.

2. The minimization of the impedance associated with ground

and power paths.

3. The inherent distributed capacitor formed by the power

–VS

plane, PCB insulation, and ground plane.

OBSOLETE Figure11. DifferentialECLforEncode

As a final alternative, the ECL gate may be replaced by an ECL

comparator. The input to the comparator could then be a logic

signal or a sine signal.

AD96687 (1/2)

50⍀

510⍀

0.1␮F

0.1␮F

510⍀

ENCODE

AD10265

ENCODE

–VS

Figure 12. ECL Comparator for Encode

USING THE FLEXIBLE INPUT

The AD10265 has been designed with the user’s ease of operation

These characteristics result in both a reduction of electromagnetic

interference (EMI) and an overall improvement in performance.

It is important to design a layout that prevents noise from coupling

to the input signal. Digital signals should not be run in parallel

with input signal traces and should be routed away from the

input circuitry. The AD10265 does not distinguish between

analog and digital ground pins as the AD10265 should always

be treated as an analog component. All ground pins should be

connected together directly under the AD10265. The PCB

should have a ground plane covering all unused portions of the

component side of the board to provide a low impedance path

and manage the power and ground currents. The ground plane

should be removed from the area near the input pins to reduce

stray capacitance.

LAYOUT INFORMATION

The schematic of the evaluation board (Figure 13) represents

in mind. Multiple input configurations have been included on

a typical implementation of the AD10265. The pinout of the

board to allow the user a choice of input signal levels and input AD10265 is very straightforward and facilitates ease of use and

impedance. While the standard inputs are ±0.5 V, ±1.0 V, and

the implementation of high frequency/high resolution design

±2.0 V, the user can select the input impedance of the AD10265

practices. It is recommended that high quality ceramic chip

on any input by using the other inputs as alternate locations for capacitors be used to decouple each supply pin to ground directly

GND or an external resistor. The following chart summarizes

at the device. All capacitors can be standard high quality ceramic

the impedance options available at each input location:

chip capacitors.

AIN1 = 100 Ω when AIN2 and AIN3 Are Open.

AIN1 = 75 Ω when AIN3 Is Shorted to GND.

AIN1 = 50 Ω when AIN2 Is Shorted to GND.

Care should be taken when placing the digital output runs.

Because the digital outputs have such a high slew rate, the

capacitive loading on the digital outputs should be minimized.

AIN2 = 200 Ω when AIN3 Is Open.

AIN2 = 100 Ω when AIN3 Is Shorted to GND.

AIN2 = 75 Ω when AIN2 to AIN3 Has an External Resistor of

AIN2 = 300 Ω, with AIN 3 Shorted to GND.

AIN2 = 50 Ω when AIN2 to AIN3 Has an External Resistor of

AIN2 = 100 Ω, with AIN3 Shorted to GND.

Circuit traces for the digital outputs should be kept short and

connect directly to the receiving gate. Internal circuitry buffers

the outputs of the AD6640 ADC through a resistor network to

eliminate the need to externally isolate the device from the

receiving gate.

AIN3 = 400 Ω.

AIN3 = 100 Ω when AIN3 Has an External Resistor of 133 Ω to GND.

AIN3 = 75 Ω when AIN3 Has an External Resistor of 92 Ω to GND.

AIN3 = 50 Ω when AIN3 Has an External Resistor of 57 Ω to GND.

REV. A

–11–

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