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AD10265AZ

Dual Channel, 12-Bit, 65 MSPS A/D Converter with Analog Input Signal Conditioning

Analog Devices 

AD10265

THEORY OF OPERATION

Refer to the Functional Block Diagram. The AD10265 employs

three monolithic ADI components per channel (AD9631,

AD9632, and AD6640), along with multiple passive resistor

networks and decoupling capacitors to fully integrate a complete

12-bit analog-to-digital converter.

ENCODE

SOURCE

0.01␮F

V1

Rx

ENCODE

ENCODE

5V

R1

R2

AD10265

The input signal is first passed through a precision laser-trimmed

resistor divider, allowing the user to externally select operation

Figure 7. Lower Threshold for Encode

with a full-scale signal of ±0.5 V, ±1.0 V, or ±2.0 V by choosing

the proper input terminal for the application.

Since the AD6640 implements a true differential analog input,

V1

=

R2

5R2

+ R1Rx

to raise logic threshold.

R1+ Rx

the AD9631/AD9632 have been configured to provide a differ-

AVCC

ential input for the AD6640 ADC through ac-coupling. The ac

OBSOLETE signal gain of the AD9631/AD9632 can be trimmed to provide a

constant differential input to the AD6640. This allows the

converter to be used in multiple system applications without

the need for external gain circuit normally requiring trim. The

AD9631/AD9632 were chosen for their superior ac performance

and input drive capabilities, which have limited the ability of

many amplifiers to drive high-performance ADCs. As new

amplifiers are developed, pin-compatible improvements are

planned to incorporate the latest operational amplifier technology.

APPLYING THE AD10265

Encoding the AD10265

Best performance is obtained by driving the encode pins differ-

entially. However, the AD10265 is also designed to interface

with TTL and CMOS logic families. The source used to drive

the ENCODE pin(s) must be clean and free from jitter. Sources

with excessive jitter will limit SNR and overall performance.

Rx

ENCODE

SOURCE

V1

0.01␮F

ENCODE

ENCODE

5V

R1

R2

AD10265

Figure 8. Raise Logic Threshold for Encode

While the single-ended encode will work well for many applica-

tions, driving the encode differentially will provide increased

performance. Depending on circuit layout and system noise,

a 1 dB to 3 dB improvement in SNR can be realized. It is

recommended that differential TTL logic be used, however,

because most TTL families that support complementary outputs

are not delay or slew rate matched. Instead, it is recommended

that the encode signal be ac-coupled into the ENCODE and

ENCODE pins.

The simplest option is shown below. The low jitter TTL signal is

TTL OR CMOS

SOURCE

AD10265

ENCODE

coupled with a limiting resistor, typically 100 Ω, to the primary

side of an RF transformer (these transformers are inexpensive

and readily available; part number in Figure 9 is from Mini-

0.01␮F

ENCODE

Circuits). The secondary side is connected to the ENCODE

and ENCODE pins of the converter. Since both encode inputs

are self-biased, no additional components are required.

Figure 6. Single-Ended TTL/CMOS Encode

The AD10265 encode inputs are connected to a differential input

stage (see Figure 4 under Equivalent Circuits). With no input

connected to either ENCODE pin, the voltage divider biases the

inputs to 1.6 V. For TTL or CMOS usage, the encode source

should be connected to ENCODE. ENCODE should be

decoupled using a low inductance or microwave chip capacitor

to ground.

If a logic threshold other than the nominal 1.6 V is required,

the following equations show how to use an external resistor,

Rx, to raise or lower the trip point (see Figure 4, R1 = 17 kΩ,

R2 = 8 kΩ).

V1

=

R1R2

5R2Rx

+ R1Rx +

R2Rx

to lower

logic

threshold.

100⍀ T1–1T

TTL

ENCODE

AD10265

ENCODE

Figure 9. TTL Source—Differential Encode

A clean sine wave may be substituted for a TTL clock. In this

case, the matching network is shown below. Select a transformer

ratio to match source and load impedances. The input impedance

of the AD10265 encode is approximately 11 kΩ differentially.

Therefore “R,” shown in Figure 10, may be any value that is

convenient for available drive power.

SINE

SOURCE

T1–1T

ENCODE

R

AD10265

ENCODE

Figure 10. Sine Source—Differential Encode

–10–

REV. A

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