TC901
Dual Auto-Zeroed Operational Amplifiers
INPUT 2V
2 V/DIV 0V
01
2 3 4 5 6 7 8 9 10
1 sec/DIV
Figure 1. Input Voltage Noise
VOS (µV)
4
6
9
10
VOS
VDD (µA)
450
400
350
300
12
250
14
200
16
150
18
100
20
50
22
0
0 2 4 6 8 10 12 14 16 18 20
±VS (V)
Figure 2. VOS and IDD vs Supply Voltage
0V
OUTPUT
5 V/DIV
–15V
5 msec/DIV
Figure 3. Recovery From Negative Saturation
2V
OUTPUT
5 V/DIV
0V
OUTPUT 0V
5 V/DIV–2V
20 msec/DIV
Figure 4. Recovery From Positive Saturation
R2
R1
+15V
–
+
OUTPUT
–15V
GAIN = 40
R1= 1kΩ
R2= 40kΩ
TC901- 7 9/5/96
Figure 5. Saturation Test Circuit
+50
+40
+30
+20
+10
0
–10
–20
–30
–40
0
PHASE MARGIN
10kΩ with 50 pF LOAD
36° at 700 kHz at 70°C
40° at 800 kHz at 25°C
10
100
1k
10k
FREQUENCY (Hz)
100k
+240
+180
+120
+60
0°C
–120
–180
1M
Figure 6. Phase-Gain
4
© 2001 Microchip Technology Inc. DS21480A