DS2406 Ver la hoja de datos (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS2406 Datasheet PDF : 30 Pages
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DS2406
The TOG bit of Channel Control Byte 1 specifies if one is always reading or writing (TOG = 0) or if one
is going to change from reading to writing or vice versa after every data byte that has been sent to or
received from the DS2406 (TOG = 1). When accessing one channel, one byte is equivalent to eight reads
from or writes to the selected PIO pin. When accessing two channels, one byte is equivalent to four reads
or writes from/to each channel.
The initial mode (reading or writing) for accessing the PIO channels is specified in the IM bit. For read-
ing, IM has to be set to 1, for writing IM needs to be 0. If the TOG bit is set to 0, the device will always
read or write as specified by the IM bit. If TOG is 1, the device will use the setting of IM for the first byte
to be transmitted and will alternate between reading and writing after every byte. Table 1 illustrates the
effect of TOG and IM for one-channel as well as for two-channel operation.
THE EFFECT OF TOGGLE MODE AND INITIAL MODE Table 1
TOG IM CHANNELS
EFFECT
0
0
one channel Write all bits to the selected channel
0
1
one channel Read all bits from the selected channel
1
0
one channel Write 8 bits, read 8 bits, write, read, etc. to/from
the selected channel
1
1
one channel Read 8 bits, write 8 bits, read, write, etc. from/to
the selected channel
0
0 two channels Repeat: four times (write A, write B)
0
1 two channels Repeat: four times (read A, read B)
1
0 two channels Four times: (write A, write B), four times: (read
A, read B), write, read, etc.
1
1 two channels Four times: (read A, read B), four times: (write A,
write B), read, write, etc.
The ALR bit of Channel Control Byte 1 controls whether the activity latch of each channel gets reset.
Both activity latches are cleared simultaneously if the ALR bit is 1. They are not changed if the ALR bit
is 0. An activity latch is set with a negative or positive edge that occurs at its associated PIO channel.
Channel Control Byte 1 also controls the internal CRC generator to safeguard data transmission between
the bus master and the DS2406 for channel access. It does not affect reading from or writing to the
memory sections of the DS2406. The CRC control bits (bit 0 and bit 1) can be set to create and protect
data packets that have the size of 8 bytes or 32 bytes. If desired, the device can safeguard even single
bytes by a 16-bit CRC. This setting, however, limits the average PIO sampling rate to about one third of
its maximum possible value. The codes for the CRC control are shown in the table below.
CRC1
0
0
1
1
CRC0
0
1
0
1
Description
CRC disabled (no CRC at all)
CRC after every byte
CRC after 8 bytes
CRC after 32 bytes
The CRC provides a high level of safeguarding data. A detailed description of CRCs is found in
Application Note 27 and the “Book of DS19xx iButton Standards”. If the CRC is disabled, the CRC-
related sections in the flow chart are skipped.
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