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24AA32A-E/P

32K I2C™ Serial EEPROM

Unspecified 

24AA32A/24LC32A

32K I2C™ Serial EEPROM

Device Selection Table

Part

Number

VCC

Range

Max. Clock

Frequency

24AA32A

1.7-5.5

400 kHz(1)

24LC32A 2.5-5.5

400 kHz

Note 1: 100 kHz for VCC <2.5V

Temp.

Ranges

I

I, E

Features:

• Single supply with operation down to 1.7V for

24AA32A devices, 2.5V for 24LC32A devices

• Low-power CMOS technology:

- Active current 1 mA, typical

- Standby current 1 μA, typical

• 2-wire serial interface, I2C™ compatible

• Cascadable up to eight devices

• Schmitt Trigger inputs for noise suppression

• Output slope control to eliminate ground bounce

• 100 kHz and 400 kHz clock compatibility

• Page write time 5 ms max.

• Self-timed erase/write cycle

• 32-byte page write buffer

• Hardware write-protect

• ESD protection > 4,000V

• More than 1 million erase/write cycles

• Data retention > 200 years

• Factory programming available

• Packages include 8-lead PDIP, SOIC, TSSOP,

MSOP and DFN

• Pb-free and RoHS compliant

• Temperature ranges:

- Industrial (I): -40°C to +85°C

- Automotive (E): -40°C to +125°C

*24XX32A is used in this document as a generic part

number for the 24AA32A/24LC32A devices.

Description:

The Microchip Technology Inc. 24AA32A/24LC32A

(24XX32A*) is a 32 Kbit Electrically Erasable PROM.

The device is organized as a single block of 4K x 8-bit

memory with a 2-wire serial interface. Low-voltage

design permits operation down to 1.7V, with standby

and active currents of only 1 μA and 1 mA,

respectively. It has been developed for advanced, low-

power applications such as personal communications

or data acquisition. The 24XX32A also has a page write

capability for up to 32 bytes of data. Functional address

lines allow up to eight devices on the same bus, for up

to 256 Kbits address space. The 24XX32A is available

in the standard 8-pin PDIP, surface mount SOIC,

TSSOP, 2x3 DFN and MSOP packages.

Package Types

PDIP, MSOP

SOIC, TSSOP

A0 1

A1 2

A2 3

VSS 4

8 VCC A0

1

7 WP A1 2

6 SCL A2 3

5 SDA VSS 4

8 VCC

7 WP

6 SCL

5 SDA

DFN

A0 1

A1 2

A2 3

VSS 4

8 VCC

7 WP

6 SCL

5 SDA

Block Diagram

A0 A1 A2 WP

HV Generator

I/O

Control

Logic

Memory

Control

Logic

XDEC

EEPROM

Array

Page Latches

I/O SCL

SDA

Vcc

VSS

YDEC

Sense Amp.

R/W Control

© 2007 Microchip Technology Inc.

DS21713H-page 1

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