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FSA9280A

USB Port Multimedia Switch Featuring Automatic Select and Accessory Detection

Fairchild Semiconductor 

3. I2C

The FSA9280A integrates a fast-mode I2C slave controller

compliant with the I2C specification version 2.1 requirements.

The FSA9280A I2C interface runs up to 400KHz.

The slave address is shown in Table 2. Status information

and configuration occurs via the I2C interface.

Please see Section 9.7 for more information.

Table 2 – I2C Slave Address

Name

Size (Bits)

Slave Address

8

Bit 7

0

Bit 6

1

Bit 5

0

Bit 4

0

Bit 3

1

Bit 2

0

Bit 1

1

Bit 0

Read / Write

8bits

Slave

S Address WR A

8bits

Register

Address K

8bits

Write

Write

Write

Write

Data

Data

Data

A Data A K+1 A K+2 A K+N-1 A P

Note: Single Byte write is initiated by Master with P immediately following first data byte.

Figure 4. I2C Write Sequence

8bits

8bits

8bits

8bits

S Slave Address WR A Register Address K A S Slave Address RD A Read Data K A Read Data K+1 A Read Data K+N-1 NA P

Register address to Read specified

Single or multi byte read executed from current register location (Single Byte read is

initiated by Master with NA immediately following first data byte)

Note: If Register is not specified Master will begin read from current register. In this case only sequence showing in Red

bracket is needed

Figure 5.

I2C Read Sequence

From Master to Slave

From Slave to Master

S Start Condition

NA NOT Acknowledge (SDA High)

A Acknowledge (SDA Low) WR Write=0

RD Read =1

P Stop Condition

VBAT

VDDIO

SDA

SCL

Internal Reset Time

400µs

30ms

Idle Standby

Figure 6.

30ms

400µs

Idle Standby

I2C Reset Mode Timing

© 2009 Fairchild Semiconductor Corporation

FSA9280A • Rev 1.1.0

7

www.fairchildsemi.com

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