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PTN3460

eDP to LVDS bridge IC

NXP Semiconductors. 

NXP Semiconductors

PTN3460

eDP to LVDS bridge IC

The PTN3460 DPCD registers can be accessed by DP source through AUX channel. It

supports both Native AUX transactions and I2C-over-AUX transactions.

Native AUX transactions are used to access PTN3460 DisplayPort Configuration Data

(DPCD) registers (e.g., to facilitate Link training, check error conditions, etc.) and

I2C-over-AUX transactions are used to perform any required access to DDC bus

(e.g., EDID reads).

Given that the HPDRX pin is internally connected to GND through an integrated pull-down

resistor (> 100 k), the DP source will see HPDRX pin as LOW indicating that the

DisplayPort receiver is not ready when the device is not powered. This helps avoid raising

false events to the source. After power-up, PTN3460 continues to drive HPDRX pin LOW

until completion of internal initialization. After this, PTN3460 generates HPD signal to

notify DP source and take corrective action(s).

8.1.1 DP Link

PTN3460 is capable of operating either in DP 2-lane or 1-lane mode. The default is 2-lane

mode of operation (in alignment with PTN3460 DCPD register 00002h,

MAX_LANE_COUNT = 2).

There are two ways to enable 1-lane operation in an application:

• Connect both DP lanes of PTN3460 to the DP source. This enables the DP source to

decide/use only required number of lanes based on display resolution.

• Connect only 1 lane (DP0_P, DP0_N) to DP source and modify the DPCD register

00002h, MAX_LANE_COUNT to ‘1’ through NXP I2C configuration utility to modify the

internal configuration table. Please consult NXP for more details regarding the

Flash-over-AUX and DOS utilities.

8.1.2 DPCD registers

DPCD registers are described in VESA DisplayPort v1.1a/1.2 specifications in detail and

PTN3460 supports DPCD version 1.2.

PTN3460 configuration registers can be accessed through DP AUX channel from the

GPU/CPU, if required. They are defined under vendor-specific region starting at base

address 0x00510h. So any configuration register can be accessed at DPCD address

obtained by adding the register offset and base address.

PTN3460 supports down spreading on DP link and this is reflected in DPCD register

MAX_DOWNSPREAD at address 0003h. Further, the DP source could control

down spreading and inform PTN3460 via DOWNSPREAD_CTRL register at DPCD

register 00107h.

The key aspect is that the system designer must take care that the Input video payload fits

well within both DP link bandwidth and LVDS bandwidth (for a given pixel frequency,

SSC depths) when clock spreading is enabled. Also, another aspect for the system

designer is to ensure LVDS (panel) TCONs are capable of handling SSC modulated LVDS

signaling.

PTN3460

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 12 March 2014

© NXP Semiconductors N.V. 2014. All rights reserved.

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