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PTN3460

eDP to LVDS bridge IC

NXP Semiconductors. 

NXP Semiconductors

PTN3460

eDP to LVDS bridge IC

8.2 LVDS transmitter

The LVDS interface can operate either in Single or Dual LVDS Bus mode at pixel clock

frequencies over the range of 25 MHz to 112 MHz and color depths of 18 bpp or 24 bpp.

Each LVDS bus consists of 3/4 differential data pairs and one clock pair. PTN3460 can

packetize RGB video data, HSYNC, VSYNC, DE either in VESA or JEIDA format. To

enable system EMI reduction, the device can be programmed for center spreading of

LVDS channel clock outputs.

The LVDS interface can be flexibly configured using multi-level configuration pins (CFG1,

CFG2, CFG3, CFG4) or via register interface. The configuration pins and the

corresponding definitions are described in Table 3 through Table 6. Nevertheless, as the

configuration pins are designed for general purpose, their definitions can be modified and

they can be used for any other purposes. However, this can be achieved through firmware

upgrade only.

Table 3. CFG1 configuration options

Configuration input setting

Number of LVDS links

LOW

single LVDS bus

HIGH

dual LVDS bus

Table 4. CFG2 configuration options

3-level configuration input setting Data format

LOW

VESA

open

JEIDA

HIGH

JEIDA or VESA

Number of bits per pixel (bpp)

24 bpp

24 bpp

18 bpp

Table 5. CFG3 configuration options[1]

3-level configuration input setting LVDS clock frequency spread depth control

LOW

0%

open

1%

HIGH

0.5 %

[1] LVDS center spreading modulation frequency is kept at 32.9 kHz.

Table 6. CFG4 configuration options

3-level configuration input setting LVDS output swing (typical value)

pull-down resistor[1] to GND

250 mV

open

300 mV

pull-up resistor[1] to VDD(3V3)

400 mV

[1] Pull-up/down resistor value in the range of 1 k to 10 k.

PTN3460

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 12 March 2014

© NXP Semiconductors N.V. 2014. All rights reserved.

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