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XRT91L34

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

Exar Corporation 

XRT91L34

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

REV. 1.0.1

NAME

DLOSDIS

/SDI

LEVEL

LVTTL,

LVCMOS

TYPE

I

PIN

DESCRIPTION

39 DLOS (Digital Loss of Signal) Disable

Hardware Mode Disables internal DLOS monitoring and auto-

matic muting of RXDO[3:0]P/N recovered data output pins upon

DLOS detection. DLOS is declared when the incoming data

stream has no transition for more than 2.5µs. DLOS is cleared

when transitions are detected within a 128µs interval sliding

window.

"Low" = Monitor & Mute recovered data upon DLOS declaration

"High" = Disable internal DLOS monitoring

This pin is provided with an internal pull-down.

POL0

POL1

POL2

POL3

LVTTL,

I

LVCMOS

SDEXT0

SDEXT1

SDEXT2

SDEXT3

LVTTL,

I

LVCMOS,

REFCLKP

LVDS,

I

REFCLKN

Diff LVPECL

TTLREFCLK

LVTTL,

I

LVCMOS

Host Mode This pin is functions as the microprocessor Serial

Data Input.

126 Polarity for SDEXT Input

124 Controls the Signal Detect polarity convention of SDEXT.

36 "Low" = SDEXT is active "Low."

34 "High" = SDEXT is active "High."

NOTE: These pins have no function in Host Mode.

These pins are provided with internal pull-down.

127 Signal Detect Input from Optical Module

125 When inactive, it will immediately declare a Loss of Signal

35 (LOS) condition and assert LOS register bit and mute the activ-

33

ity of the RXDO[3:0]P/N serial data output on the respective

channel.

"Active" = Normal Operation

"Inactive" = LOS Condition (SDEXT detects signal absence)

These pins are provided with internal pull-down.

117 Reference Clock Input (77.76 MHz or 19.44 MHz)

118 This differential reference clock input will accept either a 77.76

MHz or a 19.44 MHz LVDS/Differential LVPECL clock source.

Pin CDRREFSEL determines the value used as the reference.

See Pin CDRREFSEL for more details. REFCLKP/N inputs are

internally biased to 1.2V via 15kΩ resistance. These pins are

equipped with a 100Ω line-to-line internal termination.

NOTE: In the event that TTLREFCLK LVTTL/LVCMOS input is

used instead of these differential inputs for clock

reference, the REFCLKP should be left unconnected

and REFCLKN should be tied to GND.

120 TTL Reference Clock Input (77.76 MHz or 19.44 MHz)

This optional single-ended clock input reference can be used

instead of the differential REFCLKP/N input. It will accept

either a 77.76 MHz or a 19.44 MHz LVTTL clock source. Pin

CDRREFSEL determines the value used as the reference. See

Pin CDRREFSEL for more details.

NOTE: In the event that REFCLKP/N differential inputs are

used instead of this LVTTL/LVCMOS input for clock

reference, the TTLREFCLK should be tied to ground.

This pin is provided with an internal pull-down.

8

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