XRT91L33 Ver la hoja de datos (PDF) - Exar Corporation
Número de pieza
componentes Descripción
Fabricante
XRT91L33 Datasheet PDF : 16 Pages
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REV. V1.0.0
NAME
SIGD
TEST
CAP-
CAP+
VSSA
VDDA
LEVEL
LVPECL
LVTTL
Analog
Analog
PWR
PWR
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
TYPE
I
I
I
I
PWR
PWR
PIN
DESCRIPTION
15 Signal detect. SIGD should be connected to the SIGD output
on the optical module. SIGD is active HIGH. When SIGD is set
HIGH, it means there is sufficient optical power. When SIGD is
LOW, this indicates an LOS condition, the RXCLKOP/N output
signal will be held to within +/- 500 ppm of the REFCK input.
Additionally, the RXDOP/N will be held in the LOW state.
16 Used for production testing. Set to VSS for normal operation.
17 Negative side of the external loop filter. The loop filter capacitor
should be connected to these pins. The capacitor value should
be 1.0 μF +/- 10 %
18 Positive side of the external loop filter. The loop filter capacitor
should be connected to these pins. The capacitor value should
be 1.0 μF +/- 10 %.
19 Ground pin
20 3.3V power supply
5
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