XM28C020 Ver la hoja de datos (PDF) - Xicor -> Intersil

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XM28C020

5 Volt, Byte Alterable E2PROM

Xicor -> Intersil 

XM28C020

THE TOGGLE BIT I/O6

Figure 4. Toggle Bit Bus Sequence

LAST

WE WRITE

CE

OE

I/O6

VOH

*

VOL

* Beginning and ending state of I/O6 will vary.

Figure 5. Toggle Bit Software Flow

LAST WRITE

LOAD ACCUM

FROM ADDR n

COMPARE

ACCUM WITH

ADDR n

HIGH Z

*

READY

3872 FHD F12

The Toggle Bit can eliminate the software housekeeping

chore of saving and fetching the last address and data

written to a device in order to implement DATA Polling.

This can be especially helpful in an array comprised of

multiple XM28C020 memories that is frequently up-

dated. The timing diagram in Figure 4 illustrates the

sequence of events on the bus. The software flow

diagram in Figure 5 illustrates a method for testing the

Toggle Bit.

COMPARE

NO

OK?

YES

READY

3872 FHD F13

5

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