SLB0587 Ver la hoja de datos (PDF) - Infineon Technologies
Número de pieza
componentes Descripción
Fabricante
SLB0587 Datasheet PDF : 22 Pages
| |||
SLB 0587
Interference Immunity
Components C 3, C 6 and R 3 (figure 4) provide for a stable operating voltage and thus for error-
free working of the circuit, even in the presence of high frequency line interferences (e.g.
caused by cutting in and out of mainly active loads).
In the event of short line interruption (≤ 200 ms) the set circuit state with the external wiring
shown in figure 4 will be maintained. After prolonged line outages (V S ≤ – 3.6 V) the circuit will
go into the OFF-state.
Upon line outage the synchronization of the internal logic with the line is lost. If the line outage
lasts less than three line cycles, the phasing in of the PLL becomes visible by a brief flickering.
The setting of the PLL can be influenced within certain limits by the selection that is made with
C 5 and R 10. In general terms, smaller ratings for C 5 and larger ratings for R10 will produce shorter
settling times of the PLL.
With more inert PLL characteristics there are slightly better values for rippe-control stability
(visible fluctuations in brightness when operating incandescent lamps and with ripple-control
signal on the line).
If line outages last more than three line cycles, there is blanking for approx. 200 ms after the
line recovers so that the settling process of the PLL is not visible.
Operation of Extensions
Long extension lines in installations cause voltages to be coupled in because of their stray
capacitances and phase capacitances. Internal limiting structures and appropriate evaluating
logic ensure that the circuit can work without interference for stray and phase capacitances up
to 100 nF. Even voltage drops up to 10 V in the phase conductor between the circuit and the
extension button being in phase with the dimming voltage have no effect on the working of the
circuit.
Especially at operation with long extension lines, the RC-network R 10, C5 should be connected
between pins 3 and 7 (figure 4).
Semiconductor Group
8
Share Link: 