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SAA7128H

Digital video encoder

Philips Electronics 

Philips Semiconductors

Digital video encoder

Product specification

SAA7128H; SAA7129H

Table 8 Subaddress 28H

BIT

SYMBOL

7

DECCOL

6

DECFIS

5

BS5

4

BS4

3

BS3

2

BS2

1

BS1

0

BS0

DESCRIPTION

0 = disable colour detection bit of RTCI input

1 = enable colour detection bit of RTCI input; bit RTCE must be set to logic 1 (see

Fig.22)

0 = field sequence as FISE in subaddress 61

1 = field sequence as FISE bit in RTCI input; bit RTCE must be set to logic 1 (see

Fig.22)

starting point of burst in clock cycles

PAL: BS[5:0] = 33 (21H); default value after reset

NTSC: BS[5:0] = 25 (19H)

Table 9 Subaddress 29H

BIT

SYMBOL

7

−

6

−

5

BE5

4

BE4

3

BE3

2

BE2

1

BE1

0

BE0

DESCRIPTION

These 2 bits are reserved; each must be set to logic 0.

ending point of burst in clock cycles

PAL: BE[5:0] = 29 (1DH); default value after reset

NTSC: BE[5:0] = 29 (1DH)

Table 10 Subaddress 2AH

BIT

SYMBOL

DESCRIPTION

7 to 0

CG[07:00]

LSB of the byte is encoded immediately after run-in, the MSB of the byte has to carry

the CRCC bit, in accordance with the definition of copy generation management system

encoding format.

Table 11 Subaddress 2BH

BIT

7 to 0

SYMBOL

CG[15:08]

DESCRIPTION

Second byte; the MSB of the byte has to carry the CRCC bit, in accordance with the

definition of copy generation management system encoding format.

2000 Mar 08

18

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