CMX980AL7 Ver la hoja de datos (PDF) - MX-COM Inc

Número de pieza

componentes Descripción

Fabricante

CMX980AL7

Digital Radio Baseband Processor

MX-COM Inc  

Digital Radio Baseband Processor

10

CMX980A Advance Information

4.3.1 Modulator

This takes the 2-bit symbols, performs a Gray Code conversion and uses a recursive adder to generate a 3-

bit code representing the 8 possible phase states. A look up table provides the digitally encoded I and Q

values for each phase state. The modulator function can be by-passed if required; in this case, the 3-bit code

representing the 8 possible phase states which are passed to the look up table is provided directly via the

serial interface.

4.3.2 Filters

Digital filtering is applied to the data from the modulator by two programmable FIR filters. The first has 79-taps

and provides stop band rejection and sampling correction. The second has 63-taps and provides the primary

Root Raised Cosine (RRC) shaping with Roll-off factor (α) of 0.35, together with correction for droop in the

switched capacitor reconstruction filter. These FIR filters operate at eight times the incoming symbol rate and

are configured as two filters in cascade for each I and Q channel.

4.3.3 Gain Multiplier

This feature allows user control of the signal amplitudes in the I and Q channels independently. The multiplier

provides a resolution of 11 bits; i.e. the gain is adjustable in steps of 1/2048 of maximum level. Additional

logic allows a mode of operation that will enable ramping up to the set signal level, stay at this value while

instructed by the user, then ramp back down to zero. The maximum value for each channel, the ramping up

rate and the ramping down rate are all programmable via the serial interface.

4.3.4 Offset Adjust

Offset registers allow any offsets introduced in the analog sections of the transmit path to be corrected

digitally via the serial interface. The offset adjust is independently applied to each of the I and Q channels.

The adjustment range is plus and minus full scale in each section with a resolution of 1 LSB. Thus, care must

be exercised by the user to avoid excessive offsets being applied to the Sigma-Delta DAC.

4.3.5 Sigma-Delta D-A Converters and Reconstruction Filters

The converters are designed to have low distortion and >80dB dynamic range. These 2nd order converters

operate at a frequency of 128 x symbol rate so as to over-sample the data at their inputs a further 16 times.

The reconstruction filters are 3rd order, switched capacitor, low pass filters designed to work in conjunction

with an external RC.

4.3.6 Phase Pre-distortion

A further feature allows the user to compensate for a non-orthogonal carrier phase in the external quadrature

modulator by adding a programmable fraction of up to 1/8 of the filtered I and Q channel signals to each other

immediately prior to the DAC input.

4.3.7 Ramping Output Amplitude

A facility is provided to allow ramping of the outputs in two modes. When enabled by the user, the signal from

the gain multiplier stage is multiplied by an envelope value. The value in this register, increments or

decrements at a rate programmed by the user, which is held in the TxRampUpInc and TxRampDnDec

Registers respectively.

The ramping envelope can be selected by the user to be linear or non-linear. In non-linear mode, the

envelope function is sigmoidal, minimizing spectrum spread whilst fast ramping is in operation. The RCR is a

11-bit register (not user accessible), representing a value from 0 to 1.0, which can be incremented by the

value TxRampUpInc until the count of 2047 (1.0) is reached, or decremented by the value in TxRampDnDec

until zero is reached.

In linear mode, this value (RCR) is used directly to provide the envelope amplitude, whilst in non-linear mode

it is input to a look-up table of the sigmoidal function, which in turn provides the envelope amplitude. Ramping

begins from zero when the user applies valid transmission data with the TxRampUp bit in the TxData Register

set and continues in increments of TxRampUpInc until the set gain level (see Section 4.3.3) is reached. To

begin the ramp down phase of a transmit burst the user writes post-amble data with the TxRampUp bit

cleared then the RCR decrements by an amount TxRampDnDec until the result is less than or equal to zero,

whereupon the gain is set to zero. Internal flag registers are available to indicate to the user that ramp down is

complete.

The TxRampUpInc and TxRampDnDec Registers are both 9-bit words input via the serial interface prior to the

start of a transmission; this gives programmable ramping rates from 0.125 to 64 symbol-times.

2000 MX-COM, Inc.

www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054

Doc. 20480201.001

4800 Bethania Station Road, Winston-Salem, NC 27105-1201, USA

All trademarks and service marks are held by their respective companies

Share Link: